PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 356

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Transmit Control 1 (Read/Write)
Value after reset: 9C
XC1
XCO(7:0)
Data Sheet
XCO7
7
A write access to this address resets the transmit elastic buffer to its
basic starting position. Therefore, updating the value should only be
done when the FALC56 is initialized or when the buffer should be
centered. As a consequence a transmit slip will occur.
Transmit Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX/XMFS is active.
Calculation of delay time T (SCLKX cycles) depends on the value X
of the transmit offset register XC(1:0):
system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)
0
5
with maximum delay = (256
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
with SD = 2.048 Mbit/s (system clocking n
or
system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)
0
5
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
SD = 1.544 Mbit/s (system clocking n
with BF = basic frequency = 1.544 MHz
T = Time between the active edge of SCLKX after SYPX pulse begin
and beginning of the next frame (F-bit, channel phase 0), measured
in number of SCLKX clock intervals; maximum delay:
T
See
max
H
T
T
T
T
page 178
= (200
4: X = 4 - T
maximum delay:X = 256
4: X = 3 - T + 7
maximum delay:X = 200
SC/BF) - (7
for further description.
356
SC/BF
SC/BF) - 1
SC/SD) -1
SC/SD - T + 4)
SC/BF - T + 3
1.544 MHz)
2.048 MHz)
T1/J1 Registers
XCO0
FALC56 V1.2
0
PEB 2256
2002-08-27
(23)