PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 379

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

DXSS
Clock Mode Register 2 (Read/Write)
Value after reset: 00
CMR2
DCOXC
DCF
Data Sheet
7
DCO-X Synchronization Clock Source
0 =
1 =
DCO-X Center-Frequency Enable
0 =
1 =
DCO-R Center- Frequency Disabled
0 =
1 =
H
The DCO-X circuitry synchronizes to the internal reference
clock which is sourced by SCLKX/R or RCLK. Since there are
many reference clock opportunities the following internal
prioritizing in descending order from left to right is realized:
LIM1.RL > CMR1.DXSS > LIM2.ELT > current working clock of
transmit system interface.
If one of these bits is set the corresponding reference clock is
taken.
DCO-X synchronizes to an external reference clock provided
on pin XP(A to D) pin function TCLK, if no remote loop is active.
TCLK is selected by PC(4:1).XPC(3:0) = 0011
The center function of the DCO-X circuitry is disabled.
The center function of the DCO-X circuitry is enabled.
DCO-X centers to 1.544 MHz related to the master clock
reference (MCLK), if reference clock (e.g. SCLKX) is missing.
The DCO-R circuitry is frequency centered
- in master mode if no 1.544 or 2.048 MHz reference clock on
pin SYNC is provided or
- in slave mode if a loss-of-signal occurs in combination with no
1.544 or 2.048 MHz clock on pin SYNC or
- a gapped clock is provided on pin RCLKI and this clock is
inactive or stopped.
The center function of the DCO-R circuitry is disabled. The
generated clock (DCO-R) is frequency frozen in that moment
when no clock is available on pin SYNC or pin RCLKI. The
DCO-R circuitry starts synchronization as soon as a clock on
pins SYNC or RCLKI appears.
DCOXC
DCF
379
IRSP
IRSC
IXSP
T1/J1 Registers
B
FALC56 V1.2
IXSC
0
PEB 2256
2002-08-27
(45)