PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 86

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
TABLE 9-2:
DS41350C-page 84
PORTA
LATA
TRISA
ANSEL
SLRCON
IOCA
WPUA
UCON
INTCON
INTCON2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
Name
2:
3:
RA<5:4> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RA1 and RA0 are only available as port pins when the USB module is disabled (UCON<3> = 0).
GIE/GIEH PEIE/GIEL
RABPU
ANS7
Bit 7
—
—
—
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
INTEDG0 INTEDG1 INTEDG2
PPBRST
ANS6
Bit 6
—
—
—
—
—
—
TRISA5
LATA5
TMR0IE
WPUA5
IOCA5
RA5
ANS5
Bit 5
SE0
—
(1)
(1)
(1)
TRISA4
LATA4
PKTDIS
WPUA4
INT0IE
Preliminary
IOCA4
RA4
ANS4
Bit 4
—
(1)
(1)
(1)
WPUA3
IOCA3
USBEN
RA3
RABIE
ANS3
Bit 3
—
—
—
—
(2)
(2)
(2)
RESUME SUSPND
TMR0IP
TMR0IF
SLRC
Bit 2
—
—
—
—
—
—
IOCA1
INT0IF
RA1
SLRB
Bit 1
© 2009 Microchip Technology Inc.
—
—
—
—
—
(3)
(3)
IOCA0
RA0
RABIF
RABIP
SLRA
Bit 0
—
—
—
—
—
(3)
(3)
Values on
Reset
page
282
282
282
282
282
282
282
282
279
279