PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 203

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 16-12:
TABLE 16-8:
© 2009 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON ABDOVF
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
Name
CREN bit
SREN bit
bit SREN
RCIF bit
RXREG
RX/DT
Write to
Read
pin
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
CSRC
SPEN
Bit 7
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit 0
bit 1
DTRXP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
PIC18F1XK50/PIC18LF1XK50
bit 2
CKTXP
INT0IE
Preliminary
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
bit 3
ADDEN
SENDB
BRG16
RABIE
SSPIF
SSPIE
SSPIP
Bit 3
bit 4
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
bit 6
bit 7
TMR1IF
TMR1IE
TMR1IP
ABDEN
RABIF
RX9D
TX9D
Bit 0
DS41350C-page 201
on page
Values
Reset
279
282
282
282
281
281
281
281
281
281
‘0’