PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 204

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
16.4.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
16.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
TABLE 16-9:
DS41350C-page 202
INTCON
PIR1
PIE1
IPR1
RCSTA
TRISC
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Name
are
SYNCHRONOUS SLAVE MODE
EUSART Synchronous Slave
Transmit
EUSART Transmit Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
TRISC7
CSRC
SPEN
Bit 7
identical
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
—
—
—
TRISC6
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
(see
Section 16.4.1.3
TRISC5
DTRXP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
Preliminary
TRISC4
CKTXP
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
ADDEN
TRISC3
SENDB
BRG16
RABIE
SSPIF
SSPIE
SSPIP
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
16.4.2.2
1.
2.
3.
4.
5.
6.
7.
Bit 3
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
BRGH
FERR
transmission
Bit 2
—
Synchronous Slave Transmission
Set-up:
TMR2IE
TMR2IP
TMR2IF
TRISC1
INT0IF
OERR
TRMT
WUE
Bit 1
© 2009 Microchip Technology Inc.
by
writing
TMR1IF
TMR1IE
TMR1IP
TRISC0
ABDEN
RABIF
RX9D
TX9D
Bit 0
the
on page
Values
Reset
Least
282
282
282
281
282
281
281
279
281
281
281