PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 68

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
REGISTER 7-2:
DS41350C-page 66
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
RABPU
R/W-1
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
RABPU: PORTA and PORTB Pull-up Enable bit
1 = All PORTA and PORTB pull-ups are disabled
0 = PORTA and PORTB pull-ups are enabled provided that the pin is an input and the corresponding
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
RABIP: RA and RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
INTEDG0
R/W-1
WPUA and WPUB bits are set.
INTCON2: INTERRUPT CONTROL 2 REGISTER
W = Writable bit
‘1’ = Bit is set
INTEDG1
R/W-1
INTEDG2
R/W-1
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
TMR0IP
R/W-1
© 2009 Microchip Technology Inc.
x = Bit is unknown
U-0
—
RABIP
R/W-1
bit 0