PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 273
PIC18F13K50-E/P
Manufacturer Part Number
PIC18F13K50-E/P
Description
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F13K50-EP.pdf
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23.0
The PIC18F1XK50/PIC18LF1XK50 devices differenti-
ate between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 3.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
FIGURE 23-1:
© 2009 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: See Table 23-2 for time-out situations.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
RESET
2: PWRT and OST counters are reset by POR and BOR. See Sections 23.3 and 23.4.
LFINTOSC
Instruction
RESET
OST/PWRT
Pointer
32 μs
Stack
( )_IDLE
Brown-out
Time-out
V
Detect
Sleep
DD
WDT
Reset
Rise
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
(2)
POR Pulse
BOREN
(2)
1024 Cycles
65.5 ms
PIC18F1XK50/PIC18LF1XK50
Preliminary
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 23-1.
23.1
Device Reset events are tracked through the RCON
register (Register 23-1). The lower five bits of the reg-
ister indicate that a specific Reset event has occurred.
In most cases, these bits can only be cleared by the
event and must be set by the application after the
event. The state of these flag bits, taken together, can
be read to indicate the type of Reset that just occurred.
This is described in more detail in Section 23.6 “Reset
State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 7.0
Section 23.4 “Brown-out Reset (BOR)”.
RCON Register
“Interrupts”.
S
R
BOR
DS41350C-page 271
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(1)
in
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