PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 178

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
TABLE 15-4:
DS41350C-page 176
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
SSPADD
SSPBUF
SSPCON1
SSPCON2
SSPMSK
SSPSTAT
TRISB
Legend:
Name
— = unimplemented, read as ‘0’. Shaded cells are not used by I
SSP Address Register in I
SSP Receive Buffer/Transmit Register
OSCFIP
OSCFIE
OSCFIF
TRISB7
WCOL
GCEN
MSK7
Bit 7
SMP
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH I
ACKSTAT
SSPOV
TRISB6
MSK6
ADIP
ADIE
Bit 6
ADIF
C1IP
C1IF
C1IE
CKE
2
SSPEN
ACKDT
TRISB5
C™ Slave Mode. SSP Baud Rate Reload Register in I
MSK5
RCIP
RCIF
RCIE
Bit 5
C2IP
C2IF
C2IE
D/A
TRISB4
ACKEN
Preliminary
MSK4
EEIP
EEIE
Bit 4
TXIP
TXIF
TXIE
EEIF
CKP
P
SSPM3
SSPIP
SSPIE
SSPIF
BCLIP
BCLIF
BCLIE
RCEN
MSK3
Bit 3
S
–
2
CCP1IP
CCP1IE
C™.
CCP1IF
SSPM2
USBIP
USBIF
USBIE
MSK2
Bit 2
PEN
R/W
2
C™
–
TMR2IP
TMR2IF
TMR2IE
TMR3IP
TMR3IF
TMR3IE
SSPM1
RSEN
© 2009 Microchip Technology Inc.
MSK1
Bit 1
UA
–
2
C Master Mode.
TMR1IP
TMR1IF
TMR1IE
SSPM0
MSK0
Bit 0
SEN
BF
–
–
–
–
on page
Values
Reset
282
282
282
282
282
282
280
280
280
280
282
280
282