PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 238

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
19.5.3
Exiting Sleep and Idle modes by Reset causes code
execution to restart at address 0. See Section 23.0
“Reset” for more details.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator. Exit
delays are summarized in Table 19-2.
TABLE 19-2:
DS41350C-page 236
Note 1:
T1OSC or LFINTOSC
Primary Device Clock
2:
3:
4:
(PRI_IDLE mode)
before Wake-up
Clock Source
HFINTOSC
(Sleep mode)
T
required delays (see Section 19.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
T
Execution continues during the HFINTOSC stabilization period, T
EXIT BY RESET
CSD
OST
None
is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other
is the Oscillator Start-up Timer. t
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(2)
(1)
after Wake-up
Clock Source
HFINTOSC
HFINTOSC
HFINTOSC
HFINTOSC
LP, XT, HS
LP, XT, HS
LP, XT, HS
LP, XT, HS
EC, RC
EC, RC
EC, RC
EC, RC
HSPLL
HSPLL
HSPLL
HSPLL
PLL
Preliminary
is the PLL Lock-out Timer (parameter F12).
(2)
(1)
(1)
(1)
19.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• the primary clock source is not any of the LP, XT,
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval T
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
is not stopped and
HS or HSPLL modes.
CSD
T
T
T
OST
OST
OST
Exit Delay
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
T
T
T
T
T
T
T
T
T
IOBST
IOBST
IOBST
following the wake event is still required
None
CSD
CSD
CSD
CSD
OST
OST
OST
+ t
+ t
+ t
(1)
(3)
PLL
(1)
(4)
PLL
(1)
(3)
PLL
(1)
.
(4)
(4)
(3)
(3)
(3)
© 2009 Microchip Technology Inc.
Clock Ready Status
Bit (OSCCON)
OSTS
OSTS
OSTS
OSTS
IOSF
IOSF
IOSF
IOSF