PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 112

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
13.1
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
FIGURE 13-1:
DS41350C-page 110
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Timer3 Operation
T1OSI
CCP1 Select from T3CON<3>
Timer1 Oscillator
CCP1 Special Event Trigger
TIMER3 BLOCK DIAGRAM
T1OSCEN
T3CKPS<1:0>
T3SYNC
TMR3ON
(1)
TMR3CS
Internal
Clock
F
OSC
/4
Preliminary
1
0
Timer1 Clock Input
Clear TMR3
Prescaler
1, 2, 4, 8
The operating mode is determined by the clock select
bit, TMR3CS of the T3CON register. When TMR3CS is
cleared (= 0), Timer3 increments on every internal
instruction cycle (F
increments on every rising edge of the Timer1 external
clock input or the Timer1 oscillator, if enabled.
As with Timer1, the digital circuitry associated with the
RC1/T1OSI and RC0/T1OSO/T13CKI pins is disabled
when the Timer1 oscillator is enabled. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
2
TMR3L
Sleep Input
Synchronize
OSC
Detect
High Byte
/4). When the bit is set, Timer3
TMR3
© 2009 Microchip Technology Inc.
1
0
on Overflow
TMR3IF
Set
Timer3
On/Off