PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 114

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
13.5
If CCP1 module is configured to use Timer3 and to gen-
erate a Special Event Trigger in Compare mode
(CCP1M<3:0>), this signal will reset Timer3. It will also
start an A/D conversion if the A/D module is enabled
(see Section 17.2.8 “Special Event Trigger” for more
information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR1H:CCPR1L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
TABLE 13-1:
DS41350C-page 112
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
TRISC
ANSELH
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Name
Resetting Timer3 Using the CCP
Special Event Trigger
Timer3 Register, Low Byte
Timer3 Register, High Byte
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIE
OSCFIP
OSCFIF
TRISC7
RD16
RD16
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
TRISC6
T1RUN
Bit 6
C1IF
C1IE
C1IP
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
T3CKPS1 T3CKPS0 T3CCP1
TRISC5
C2IE
C2IP
Bit 5
C2IF
—
TRISC4
INT0IE
Preliminary
EEIF
EEIE
EEIP
Bit 4
—
TRISC3
ANS11
RABIE
BCLIF
BCLIE
BCLIP
Bit 3
T3SYNC
TMR0IF
TRISC2
ANS10
USBIF
USBIE
USBIP
Bit 2
TMR1CS TMR1ON
TMR3CS TMR3ON
TMR3IF
TMR3IE
TMR3IP
TRISC1
INT0IF
ANS9
Bit 1
© 2009 Microchip Technology Inc.
CCP2IE
CCP2IP
CCP2IF
TRISC0
RABIF
ANS8
Bit 0
on page
Values
Reset
279
282
282
282
281
281
280
281
282
282