SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 76

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

7.4
Figure 7 : CPU Bus Cycle Timing - 16-bit Memory, Modified Address
This table refers to CPU bus timing when configuration input MD[5] = 1 on the falling edge of
RESET. In this case, processor address lines PA[23:2] may be connected to address inputs
LA[23:17] and A[16:2]. These inputs will be latched by the SPC8106 on the rising edge of the ALE
input pin. Note that the ALE pin should be driven by the ADS# signal from the CPU. Address
inputs A[1:0] should be connected to the ISA bus address outputs A[1:0].
Hardware Functional Specification
Symbol
SP1-34
t1
t2
t3
t4
t5
Bus Cycle Timing - 16-bit Memory (Modified Address Timing)
ADS# pulse width (ALE pin)
LA[23:17], A[16:2] valid setup to ADS# asserted
LA[23:17], A[16:2] valid hold from ADS# negated
LA[23:17], A[16:2] valid setup to MEMR#, MEMW#
asserted
A[1:0], BHE#, MEMEN valid setup to MEMR#, MEMW#
asserted
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LA[23:17]
A[16:2]
A[1:0]
BHE#
MEMEN
MEMR#
MEMW#
Table 0-23 CPU Bus Cycle Timing - 16-bit Memory, Modified Address Timing
ALE
(driven
by ADS#)
ISA bus outputs, using PA[23:2] connected to LA[23:17], A[16:2]
ADS# connected to ALE pin (MD[5] = 1 @ RESET)
Parameter
t2
t4
valid
t1
t5
X12-SP-001-07
valid
t3
Timingsource: 8106_cpu_bus16_mma_01.can
Min
30
10
10
10
0
Typ
Max
Units
411-1.0
ns
ns
ns
ns
ns
SPC8106