SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 62

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

Hardware Functional Specification
Pin Name
VSYNC#
DACRD#
DACWR#
RS2
OL[0:1]
OL23
D477
IREFEN#
MS[2:0]
SP1-20
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Type
O
O
O
O
I/O
O
O
O
I/O
*
*
*
*
*
*
*
Pin #
42
43
45
46
39, 38
35
40
47
83, 82,
71
Table 0-5 External CRT/RAMDAC Interface Pins (Continued)
Drv
TS4D
(* C)
TS3
(* C)
TS3
(* C)
TS2D
(* C)
OL0
C/
TS2
OL1
TTLS/
TS2
TS2D
(* C)
TS2
(* C)
TS2U3
(* C)
TTL/
TTL2
Description
Vertical Sync. This output is clocked out on the falling edge of PCLK
and is driven to indicate the vertical retrace period. The polarity of this
signal is determined by a control bit in register 3C2h.
RAMDAC Read Strobe. This signal goes low when a valid read
access to the VGA RAMDAC is decoded by the chip.
RAMDAC Write Strobe. This signal goes low when a valid write
access to the VGA RAMDAC is decoded by the chip.
Register Select 2 output. This output should be connected to the RS2
input of the RAMDAC (Bt477 or equivalent). The logic level on this
output may be set by setting AUX[0B] bit 3. This signal is required to
allow CPU access the control and overlay registers of the external
RAMDAC.
Multiple Function:
Overlay Select outputs 1:0
When MD[13]=0 at RESET, these pins are outputs used to provide
sprite/HW cursor function on the CRT display. In this case, these
outputs should be connected to the OL[0:1] inputs of the RAMDAC
(Bt477 or equivalent). They are used by the sprite circuitry to access
the overlay registers in the RAMDAC.
For alternate function see “Multiple Function Pin Descriptions” on
page 23.
Overlay Select output 2/3. This output should be connected to both
the OL2 and OL3 inputs of the RAMDAC (Bt477 or equivalent). This
signal is used by the sprite circuitry to access the overlay registers in
the RAMDAC.
For alternate function see “Multiple Function Pin Descriptions” on
page 23.
477 Control Signal. This output should be connected to the 477/471
input of the RAMDAC (Bt477 or equivalent). This signal is used to
access the control register of the RAMDAC and to allow it to be
powered down. The logic level on this output can be controlled by
setting AUX[0B] bit 4, and is also controlled by the power save logic.
IREF Enable output. This signal is used to control the external current
reference source required by the RAMDAC, allowing powering down
the analog circuitry when not required. When this signal is driven low,
the external current reference should be enabled. When this signal is
high, the external current reference should be shut off.
Monitor Sense inputs. These signals should be connected to the
monitor sense lines from the CRT monitor cable. The status of these
bits is readable in Auxiliary register [08] bits 2:0, and is used by BIOS
software to determine the presence and type of monitor connected.
Optionally, the SENSE output of the RAMDAC may be connected to
one of these inputs to allow the BIOS to read the SENSE signal and
detect the monitor. These pins can be forced low by the DCC2 monitor
support bits in AUX[10h] bits 1:0.
X12-SP-001-07
411-1.0
SPC8106