SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 14

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

Data Sheet
SPC8106
FUNCTIONAL BLOCK DESCRIPTION
The Sequencer
The Sequencer generates internal signals to synchronize the operation of the chip as well as the
signals to control the timing of the display DRAM. The Sequencer also arbitrates between CPU
and video display accesses to the DRAM. It contains registers that allows selection of character
font set, control the structure of the video memory and allow write masking of the individual plane
of memory.
CRT Controller
The CRT Controller generates the horizontal and vertical synchronization signals for the CRT, sin-
gle panel or dual panel LCD display and character and/or pixel addresses for display data from
DRAM.
CRT Interface
The CRT interface aligns CRT signals to the Pixel Clock and generates the I/O Control signals for
CPU access to the RAMDAC.
Address Generator
The Address Generator takes the display and refresh addresses from the CRT Controller and
converts them into RAS and CAS addresses for the display DRAM, and multiplexes these display
accesses with CPU memory accesses.
Attributes Controller
The Attributes Controller takes in pixel and attribute information from the Graphics Controller and
display DRAM and formats the data into pixel information which then passes through the lookup
table. It also controls display character attributes such as blink, underline and horizontal pixel
panning.
Graphics Controller
The Graphics Controller supplies display memory data to the Attributes Controller during display
time and provides data translation between the CPU bus and the display memory during CPU
read or write access cycles.
Display Memory Interface
The Display Memory Interface is a bridge by which the chip communicates with the DRAM. It con-
tains buffers that are used to store recently fetched DRAM data.
Memory Decoder
The Memory Decoder monitors the CPU-bus activity and decodes cycles for the display DRAM. It
supplies memory access control signals to the Sequencer.
Port Decoder
The Port Decoder decodes CPU-bus I/O cycles to provide enable and write strobes for the on-
chip I/O registers.
DS-8
411-1.0
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com