SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 279

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

8.0
In video technology the term sprite usually refers to a bitmap shape that can be moved across
complex backgrounds without flicker or damage to the background image. The SPC8106 sup-
ports a hardware assisted sprite capable of displaying a 64 x 64 pixel 4-color image, regardless of
the video mode. Typical uses for sprites are for hardware cursors in GUI environments, or pop-
ups for system status.
The intent of this document is to demonstrate the rudiments required to display and manipulate a
sprite image with the SPC8106. It is assumed the reader has an understanding of the VGA regis-
ter architecture. The code samples included are C-like and are intended to show concepts, and
have not been compiled. Most sprite control is performed through two index/data register pairs
and the sprite image is stored in unused video memory.
The first set of sprite control registers are located in the CRTC (port 3D4h/3D5h) at indexes 30h
through 38h. These indexes are beyond those defined by IBM for the VGA and control functions
such as sprite image address, screen position, and clipping.
The second set of sprite control registers are located in the Auxiliary Register (port 3DEh/3DFh)
at indexes 05h, 09h and 0Bh. These registers control sprite enable, memory mapping and sprite
color control.
The sprite image should be placed in normally unused video memory. Each sprite image requires
1KB of memory (the SPC8106 supports 512KB) so there are a possible 512 possible sprite ’slots’
in display memory. To ensure the sprite image is in unused video display memory it should be
placed in the upper 256KB. Placing the image in the lower 256KB of video memory could permit
a standard VGA memory access to overwrite the image.
The programming examples contained within this document utilize a memory technique which
swaps the upper and lower 256KB of memory. The examples also use a feature called Sprite
Write Mode. Upper page swapping permits the upper 256KB of video memory to be addressed
through the A000h segment, while swapping the normal video memory to the B000h segment.
Upper page swapping is proprietary to the SPC8106 and does not affect the display contents (to
avoid memory manager conflicts, do not update the video memory in the B000h segment). This
upper page swapping technique is consistent with the memory access methods required by previ-
ous Seiko Epson VGA LCD controllers which incorporate a hardware sprite.
Sprite Write Mode is a consistent programming interface for placing sprite image data into display
memory, this allows programming of the sprite in one consistent format no matter what current
memory model that the controller is in. This mode eliminates the complexity of setting up the
memory as depicted in the following diagram by allowing the sprite image to be envisioned as two
streams of pixel data, one stream representing the most significant bits of each pixel and the
other representing the least significant bits.
The following diagram depicts the VGA memory in a planar format and the sprite as displayed on
the screen. The two data structures represent the strings of pixel information where each bit of
Bytes 0 through 3 represent one pixel each (bits 0 through 31). The high order bits of the image
(cursor XOR mask) are placed in the even planes (planes 0 and 2) and the low order bits (AND
mask) are place in the odd planes (planes 1 and 3).
SPC8106
The sprite hardware does not support a packed pixel format. Prior to loading a sprite image, the
image data must be broken down into two arrays of pixels. This format is typical of the XOR and
AND arrays provided for the cursor image in such popular GUIs as Windows and OS/2.
411-1.0
PROGRAMMING THE SPRITE HARDWARE
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
X12-AN-003-02
Programming Notes and Examples
SP3-53