SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 122

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

Implementation Notes
Hardware Functional Specification
SP1-80
1. For Software Power Save Mode 4 and the Hardware Power Save Mode (Suspend mode), the clock source
2. For Software Power Save Mode 4 and the Hardware Power Save Mode (Suspend mode), the clock source
3. The self-refresh mode option available in Power Save Mode 4 and the Hardware Power Save Mode (Sus-
4. In Software Power Save Modes 3 and 4, software may set AUX[03] bit 4 to disable the internal clock oscilla-
5. In Hardware Power Save Mode (Suspend mode), the internal clock oscillators are automatically turned off by
6. In Hardware Power Save Mode (Suspend), if MEMEN is selected as the refresh clock source, then the inter-
7. In Hardware Power Save Mode (Suspend), if PDCLK is selected as the refresh clock source, then the inter-
8. In Hardware Power Save Mode (Suspend), if the internal active clock is used as the refresh clock source,
9. The output pin LCDPWR# should be used to control the LCD panel's power supply via external circuitry.
10. After RESET is asserted, LCDPWR# is held high until the CRTC is programmed and running (i.e. LCD inter-
11. Circuitry in the chip will ensure that upon entering a power save mode, LCDPWR# will be driven high (panel
12. Similarly, if the Sequencer is stopped, (Sequencer Reset Register bit 1 or bit 0 = 0), then LCDPWR# will be
from MEMEN should be running at a frequency of 64 kHz. MEMEN’s active low pulse width should be as
short as possible (but greater than the minimum DRAM RAS pulse width requirement). The use of a 64 kHz
clock source is required for meeting the 256 cycles/4 ms DRAM refresh specification. Optionally, an 8 kHz
clock source may be connected to MEMEN for DRAMs supporting 256 cycles/32 ms, or the 64 kHz input can
be internally divided down to 8 kHz by setting the 32/4 ms Refresh Select bit (AUX[02] bit 0 = 1).
connected to the PDCLK input can be either a 32 kHz 50% duty cycle clock, or a 64 kHz clock with duty cycle
similar to the requirement for MEMEN described above, except the 64 kHz clock should have a short high
pulse instead of low pulse as for MEMEN. The 32 kHz input clock can be accommodated in two ways; an ex-
ternal RC circuit can be utilized and be attached to pins 38, 39 with MD[13] = 1 and MD14 = 1 at RESET in
order to create an ~100ns delayed clock. This is used internally to generate a 64 kHz clock from the 32 kHz
source with the appropriate duty cycle, as required by the 64 kHz refresh rate for 256 cycles/4 ms DRAM. If
MD[14] = 0 at RESET, then the external RC circuit is not necessary and the 32 kHz clock input is doubled in-
ternally to generate a 64 kHz clock source which provides the appropriate duty cycle, as required by the 64
kHz refresh rate for 256 cycles/4 ms DRAM. The internal PDCLK is recommended as it leaves pins 38, 39
free to use as Overlay support for the CRT Sprite/HW cursor. For either type of PDCLK source input, the re-
sulting internal 64 kHz refresh rate can be internally divided down to 8 kHz to support 256 cycle/32 ms
DRAM by setting the 32/4 ms Refresh Select bit (AUX[02] bit 0 = 1).
pend mode) must only be enabled if the DRAM installed supports self-refresh operation.
tors. This can be used to further reduce system power consumption.
hardware if the self-refresh option is enabled.
nal clock oscillators are automatically turned off by hardware.
nal clock oscillators are automatically turned off by hardware.
then the internal clock oscillators cannot be turned off by hardware.
When LCDPWR# is high, the external panel power supply should be turned off. When LCDPWR# is low, the
power supply should be enabled.
face signals are active).
power shut off) before the interface signals are tri-stated or forced low. Upon exiting a power save mode,
LCDPWR# will be driven low (panel power turned on) after the interface signals are returned to their active
driving states. This sequencing of the LCDPWR# and interface signals is done to protect the panel from be-
ing damaged from DC signals applied to the interface while it is powered up.
driven high (panel power shut off) before the Sequencer is shut down and the LCD interface signals are halt-
ed. Upon restarting the Sequencer (by setting Sequencer Reset Register bit 1 and bit 0 to 1), LCDPWR# will
be driven low (panel power turned on) after the Sequencer is has started running and the LCD interface sig-
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
X12-SP-001-07
411-1.0
SPC8106