SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 58

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

5.0
Hardware Functional Specification
Pin Name
A[0:16],
LA[17:23]
ALE
D[0:15]
MEMEN
IOR#
IOW#
MEMR#
SP1-16
Key
pins marked with a * in the Type column are outputs in normal operation mode, but for pin test
mode, these outputs are placed in a high impedance state and these pins become inputs.
Therefore these pins are actually bidirectional, although only the normal output mode is shown
in this table. For these pins, the input type for this test mode is shown in parentheses (*). See
“PIN TEST MODE” on page 124 for more information.
C
TTL
TTLS
TSx
TSxUy = Tri-state CMOS level driver with pull up resistor (y=2: 100 k typical., y=3: 200 k typ.),
TSxD
PIN DESCRIPTION
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Type Pin #
I
I
I/O
I
I
I
I
= CMOS level input
= TTL level input
= TTL level input with hysteresis
= Tri-state CMOS level driver, x denotes driver type - see “D.C. CHARACTERISTICS” on
= Tri-state CMOS level driver with pull down resistor (200 k typ.), x denotes driver type
page 26 for rating.
x denotes driver type - see “D.C. CHARACTERISTICS” on page 26 for rating.
- see “D.C. CHARACTERISTICS” on page 26 for rating.
104~107,
110~122,
2~4, 5~8
102
125~140
97
94
95
96
Drv
TTL
TTL
TTL
/TS2
TTLS
TTLS
TTLS
TTLS
Table 0-1 CPU Interface Pins
Description
CPU bus address inputs. In Suspend Mode, the Address inputs are
internally masked off. If the value on MD[5] at RESET = 1, then the
ALE input pin is used to internally latch LA[19:17] and A[16:2],
allowing these address bits to be driven by the processor address
bus. If the value on MD[5] at RESET = 0, then standard ISA address
timing is assumed, where pins A[0:16], LA[17:23] should be
connected to the ISA bus signals SA[0:16], LA[17:23] respectively.
ISA Bus Address Latch Enable. In Suspend Mode the ALE input is
disabled. If the value on MD[5] at RESET = 1, then the ALE input is
used to internally latch LA[19:17] and A[16:2], allowing these address
bits to be driven by the processor address bus. In this mode, the
processor ADS# output should be connected to this pin. If the value
on MD[5] at RESET = 0, then standard ISA address timing is
assumed, and only the LA[19:17] inputs are internally latched.
16 bit ISA-Bus data bus. These lines are driven by the chip only
during read cycles, and are in a hi-Z state at all other times. In
Suspend Mode, these inputs are internally masked off.
ISA Bus Memory Enable. This signal should be connected to the
REFRESH# signal on the ISA bus. When this signal is low (e.g.
during a system memory refresh cycle), memory address decoding is
disabled.
ISA Bus I/O Read Strobe. In Suspend Mode the IOR# input is
disabled.
ISA Bus I/O Write Strobe. In Suspend Mode the IOW# input is
disabled.
ISA Bus System Memory Read Strobe. In Suspend Mode the
MEMR# input is disabled.
X12-SP-001-07
411-1.0
SPC8106