SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 61

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

SPC8106
Pin Name
P[0:7]
PCLK
BLANK#
HSYNC#
Pin Name
XSCL2
UD[0:3]
UD[4:7]
LD[0:3]
LD[4:7]
LCDPWR#
WF
a. some of these pins have alternate uses in some display modes. See “Pin Mapping for Various DRAM
411-1.0
Configurations” on page 25
Type
O
O
O
O
O
O
O
Type
O
O
O
O
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
*
*
*
*
*
*
*
*
*
*
*
Pin #
9
22~25
26~29
16~19
30~33
21
15
Pin #
26~33
34
44
41
Table 0-4 LCD Panel Interface Pins
Table 0-5 External CRT/RAMDAC Interface Pins
Drv
TS4
(* C)
TS4
(* C)
TS2D
(* C)
TS4
(* C)
TS2D
(* TTL)
TS2
(* C)
TS4D
(* C)
Drv
TS2D
(*TTL)
TS2D
(* C)
TS2D
(* C)
TS4D
(* C)
Description
This second shift clock is used together with XSCL in 8-bit single color
panel mode to shift in alternate sets of display data. XSCL2 is also
used alone as the shift clock in 8-bit dual color panel mode and 4-bit
single color panel mode.
Upper panel display data for dual panel - dual drive mode. For 8-bit
single panel-single drive mode, these bits are the most significant 4-
bits of the 8-bit output data to the panel (data[7:4]). For 4-bit single
panel mode, these bits are the 4 bits of data output to the panel. For
16-bit LCD modes, these outputs are the multiplexed upper panel
data if MD[7]=1 at RESET, or the lower nibble of the upper panel data
if MD[7]=0 at RESET.
When MD[7]=0 at RESET, these pins are the upper nibble of the 16-
bit LCD mode upper panel data.
Lower panel display data for dual panel-dual drive mode. For 8-bit
single panel-single drive mode, these bits are the least significant 4
bits of the 8-bit output data to the panel (data[3:0]). For 4-bit single
panel mode, these outputs are driven low. For 16-bit LCD modes,
these outputs are the multiplexed lower panel data if MD[7]=1 at
RESET, or the lower nibble of the lower panel data if MD[7]=0 at
RESET.
When MD[7]=0 at RESET, these pins are the upper nibble of the 16-
bit LCD mode lower panel data.
LCD power control. In normal operation this signal is driven low to
enable an external LCD power supply. This signal is driven high when
the chip is put into any power save mode, when Auxiliary Register 06
bit 0 is set to 1, or when the Sequencer is in a reset state. It can be
used externally to turn off the panel supply voltage and backlight.
After a RESET, this signal is held high until the CRTC is programmed
and running.
LCD Backplane Bias signal. This output toggles once every n LP
periods, as programmed in AUX[0D].
Description
When MD[7]=1 at RESET, these pins are the Pixel Data outputs.
These 8 bits are connected to the pixel select inputs of the external
RAMDAC.
Pixel Clock. Pixel data is clocked out of the chip on the falling edge of
PCLK.
Blank output. This output is clocked out on the falling edge of PCLK
and is driven low during display blanking periods.
Horizontal Sync. This output is clocked out on the falling edge of
PCLK and is driven to indicate the horizontal retrace period. The
polarity of this signal is determined by a control bit in register 3C2h.
X12-SP-001-07
a
(Continued)
Hardware Functional Specification
SP1-19