SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 154

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

bits 5-0
bit 7
bit 6
bits 5-0
bits 7-0
Hardware Functional Specification
10 TFT Auto-Centering Adjust Register RW (if AUX[00] bit 0 = 1)
n/a
11 TFT Supplementary Register RW (if AUX[00] bit 0 = 1)
Vertical
Panel Size
MSB
12 Vertical Panel Size Register RW (if AUX[00] bit 0 = 1)
Vertical
Panel Size
Bit 8
SP1-112
These LCD B Registers are accessed in CRTC register space by setting AUX[00] bit 0, LCD B
Registers Program Enable, to 1. Also, if CRT mode is enabled, i.e. CRT Enable, AUX[0B] bit 1 =
1, these registers are ignored. The CRTC[11h] bit 7 Protect Registers has no affect on AUX
B[01].
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
n/a
Vertical
Panel Size
LSB
Vertical
Panel Size
Bit 7
Auto Centering Adjust Bits [5:0]
This 6-bit value is added to the autocentering offset to center the image on a TFT display when the
CRT is not enabled and autocentering is enabled. Because this register affects all autocentered
(LCD) displays, it should be programmed to 0 for non-TFT displays.
Vertical Panel Size MSB
The MSB bit of the Vertical Panel Size is required to support TFT displays (i.e. displays with more
than 511 lines). For all non-TFT panels this bit should be programmed to 0.
Vertical Panel Size LSB
The LSB bit of the Vertical Panel Size is required to support TFT displays with an odd number of
lines. For all non-TFT panels this bit should be programmed to 0.
Vertical Start Bits [5:0]
This 6-bit value determines the number of blank lines following vertical retrace when CRT is not
enabled. Passive LCD panels require 0 blank lines and TFT panels typically require 32 lines. This
value has no effect when autocentering is enabled. This value should be programmed to 0 for all
non-TFT panels.
Vertical Panel Size Bits [7:0]
For dual-panel mode, this register contains the 8 most significant bits of the 9-bit number of lines in
half the panel. For single-panel mode, this register contains the 8 most significant bits of the 9-bit
number of lines in the panel. The least significant bit is always 0. For example, for a 480 line dual
panel, this register is programmed with the 8 MSB of the 9-bit binary representation of 480 2=240,
i.e. 78h. For a 480 line single panel, this register is programmed with the 8 MSB of the 9-bit binary
representation of 480 = F0h.
Auto
Centering
Adjust Bit 5
Vertical
Start Bit 5
Vertical
Panel Size
Bit 6
Auto
Centering
Adjust Bit 4
Vertical
Start Bit 4
Vertical
Panel Size
Bit 5
X12-SP-001-07
Auto
Centering
Adjust Bit 3
Vertical
Start Bit 3
Vertical
Panel Size
Bit 4
Auto
Centering
Adjust Bit 2
Vertical
Start Bit 2
Vertical
Panel Size
Bit 3
Auto
Centering
Adjust Bit 1
Vertical
Start Bit 1
Vertical
Panel Size
Bit 2
Auto
Centering
Adjust Bit 0
Vertical
Start Bit 0
Vertical
Panel Size
Bit 1
411-1.0
SPC8106