SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 141

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
SPC8106
0B Extended Function Register 3 RW
Ext Palette
Write Disable
411-1.0
Int. LUT
Write
Disable
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External Palette Write Disable
When this bit is set to 0, I/O writes to the External RAMDAC are allowed. When this bit is set to 1, I/
O writes to the External RAMDAC are masked off. This masking includes writes to the External
Write Address Register (3C8h), the Palette Data Register (3C9h), the LCD Lookup Table Pixel
Mask Register (3C6h), and the External Read Address Register (3C7h). The resultant effect is that
reads from the External RAMDAC are valid only for the last valid Read Address, and new writes
are masked off, however, the writes will affect External DAC Status Register (3C7h).
Internal LUT Write Disable
When this bit is set to 0, I/O writes to the internal LUT registers are allowed. When this bit is set to
1, I/O writes to the internal LUT are masked off (3C7h, 3C9h). Even if writes are disabled by this
bit, attempted I/O writes will still affect the LUT/RAMDAC status register.
Anti-sparkle Enable
Setting this bit to 1 enables the Anti-sparkle circuitry which copies the previous display pixel during
Look Up Table (LUT) accesses. Setting this bit to 0 disables this circuitry. This bit is intended to be
used with TFT displays.
External DAC Control Register Write Enable
This bit is used to control the logic level on output signal D477. If this bit is set to 0, then the D477
output is driven low. If this bit = 1, then the D477 output is driven high. Note that the logic level on
this pin is also controlled by power save logic and CRT mode hardware, and this bit setting may be
ignored in some modes. This bit should be set to 1 before writing to the external RAMDAC control
register, and should be reset to 0 after the control register is written.
External DAC RS2 Bit
This bit is used to control the logic level on output signal RS2. If this bit = 0, then the RS2 output is
driven low. If this bit = 1, then the RS2 output is driven high. This bit should be set to 1 before the
CPU accesses the external RAMDAC overlay and control registers. This bit should be set back to 0
for normal operation so that the standard RAMDAC palette registers may be accessed. When this
bit is set to 1, reads and writes to I/O addresses 3C6h, 3C8h, and 3C9h will not access the 256
VGA palette locations in the internal LCD LUT, but instead will allow access the internal sprite pal-
ette registers, or external RAMDAC overlay registers.
External DAC Read Select
The External DAC Read Select bit is used to enable reads of the external RAMDAC palette and
overlay registers. When this bit = 0, reads to 3C6h, 3C8h, and 3C9h return values from the internal
LCD gray scale lookup table registers or sprite palette. When this bit = 1, then reads to these
addresses are decoded as external RAMDAC palette or overlay register reads. This bit should be
set to 1 if an external RAMDAC is present.
CRT Enable
When the CRT Enable bit = 1, CRT display hardware is enabled. When this bit = 0, CRT display
hardware is disabled. This bit will be initialized to 0 on RESET. This bit works in conjunction with
LCD Enable and TFT Enable. See the following table.
Anti-sparkle
Enable
Ext. DAC Ctl
Reg Write
Enable/
D477
X12-SP-001-07
Ext. DAC
RS2 Bit
Ext. DAC
Read Select
Hardware Functional Specification
CRT Enable LCD Enable
SP1-99