SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 136

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

bit 3
bits 2-0
bits 7-0
Hardware Functional Specification
04 General Storage and Test Register 0 RW
Test Input
Select
Bit 3
SP1-94
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Test Input
Select
Bit 2
Aux Reg Only Decode
The Aux Reg Only Decode bit is intended for use by power save mode software. In power save
modes, this bit may be set to 1 to disable all I/O access decoding except to the Auxiliary Registers.
Note that setting this bit to 1 would normally be useful only when in Power Save Modes 3 or 4. At all
other times this bit should be set to 0 to enable all I/O address decoding.
Power Save Mode Select Bits [2:0]
These bits are used to select 1 of 5 software power save modes. When these bits are set
to 000, 110, or 111 then the chip operates in normal active mode. Binary values of 001,
010, 011, 100, or 101 written to these bits cause the chip to enter power save modes 1, 2,
3, 4 or 5 respectively. If the SUSPEND# input pin is low, then the power save mode setting
in this register is ignored.
effect.
General Storage and Test Bits
For normal operation, AUX[00] bit 4 (Test Mode Enable) is set to 0, and then the General Storage
and Test Register can be used to provide 8 bits of read/write temporary storage. In normal opera-
tion mode these bits have no effect on hardware.
Caution
When the Test Mode Enable bit is set to 1 the chip is placed in
a special test mode and this register is used to select various
internal test functions.
Test Input
Select
Bit 1
Test Input
Select
Bit 0
If CRT mode is enabled, programming power save mode 5 has no
X12-SP-001-07
Test Output
Select
Bit 3
Test Output
Select
Bit 2
Test Output
Select
Bit 1
Test Output
Select
Bit 0
411-1.0
SPC8106