SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 134

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

bit 7
bits 6-4
bits 3-2
Hardware Functional Specification
02 LCD Support Register 1 RW
CRT Sprite
Enable
Panel Description
8 bit Dual Monochrome
8 bit Single Monochrome
4 bit Single Monochrome
8 bit Single Color
8/16
Color
16 bit Single Color
9 bit color TFT
12 bit color TFT
12 bit RGB
RGBI
SP1-92
a. 16-bit panels require external circuitry for DoubleScan compatibility.
a
bit Dual Color/4 bit Single
X bits are DON’T CARE
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Panel
Config
Bit 3
CRT Sprite Enable
The CRT Sprite Enable bit is used to enable or disable the sprite display on the CRT monitor. When
this bit = 0, the sprite will not be displayed on the CRT monitor. When this bit = 1 and AUX[05] bit 5
= 1, the sprite circuitry for the CRT display is enabled and it will be possible to display the sprite on
the CRT monitor, provided that the value on MD[13] = 0 at RESET to allow use of the OL1 and OL0
output pins.
Panel Configuration Bits [3:1]
The following table describes the function of the Panel Configuration Bits [3:0]. Bit 0 is located in
AUX[01] bit 0 (see above).
PSM4/S Refresh Clock Select Bits [1:0]
These bits are used to select the refresh clock source during Power Save Mode 4 or Suspend
mode, according to the following table:
CLKI1, CLKI2
When this option is selected, then the active pixel input clock (CLKI1 or CLKI2) is used to generate
all Power Save mode refresh timing. The active pixel clock is determined by the Clock Select bits in
Misc Output Register (3C2), and by the LCD Enable and CRT Enable bits in AUX[0B].
PSM4/S Refresh
Clock Select 1
Panel
Config
Bit 2
0
0
1
1
Table 0-51 Panel Configuration Bit Table
Config Bit 3
AUX [02] b6
Table 0-52 PSM4/S Refresh Clock Select
Panel
0
0
0
1
1
1
1
1
1
1
Panel
Config
Bit 1
PSM4/S Refresh
Clock Select 0
Config Bit 2
AUX [02] b5
X12-SP-001-07
0
1
0
1
Panel
PSM4/S
Refresh Clk
Select Bit 1
X
X
X
X
0
0
0
0
1
1
Refresh Clock Source in
Power Save Mode 4 and
Suspend
Config Bit 1
AUX [02] b4
Panel
PSM4/S
Refresh Clk
Select Bit 0
X
X
X
X
X
X
0
0
1
0
CLKI1, CLKI2
Self Refresh
MEMEN
PDCLK
Config Bit 0
AUX [01] b0
LCD Signal
PS Mode
State
Panel
0
1
1
1
0
1
1
1
0
0
b7
0
0
0
0
0
0
0
0
0
1
32/4 ms
Refresh
Select
AUX[00]
Bits
411-1.0
b6
0
0
0
0
0
0
0
1
1
0
SPC8106
b5
0
0
0
0
0
0
1
1
0
0