SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 270

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

4.0
To set a powerdown mode, one has to assume the worst case scenario, i.e. we already are in a
powerdown mode, the oscillator is disabled and only ports 3DEh/3DFh are decoded. Every pow-
erdown sequence therefore first powers the chip up to a known state and then powers the chip
down to the requested state. Note that a small delay is needed after the oscillator is re-enabled,
this is to accommodate for the fact it takes a finite amount of time for the oscillators to start oscil-
lating after being enabled.To avoid any visual anomalies or to ensure proper powerdown timings,
most powerdown sequences wait for several frames, this is accomplished by counting vertical
retraces. (To do this, we must have full address decoding enabled.)
Powerdown sequences are summarized in the following “merge” tables. The format of the table is
port (only the low byte is required, as the upper is implicitly 3), register index, AND mask, OR
mask. If the “port” value is 0xFF a time delay is inserted, if the “port” value is 0xFE, we wait for
one vertical retrace.
Also note the powerdown Mode 4 comes in two flavors, if we have any PD clock, we can disable
the oscillator. If the PD clock is CLOCKI, we cannot disable the oscillator, as we would in essence
disable the PD clock itself. The presence of the PD clock is determined at run-time based on the
MD lines.
aStateLCD_0
aStateLCD_1
aStateLCD_2
aStateLCD_3
aStateLCD_4
Programming Notes and Examples
SP3-44
MANUAL SETTING OF POWER STATES ON THE SPC8106
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
DB
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0DEh,03h,11000111b,00000000b ; Addr Decode,Osc. enable
0FFh
0FEh
0DEh,03h,11111000b,00000000b ; p.mode 0
0
0DEh,03h,11000111b,00000000b ; Addr Decode,Osc. enable
0FFh
0DEh,03h,11111000b,00000001b ; p.mode 1
0
0DEh,03h,11000111b,00000000b ; Addr Decode,Osc. enable
0FFh
0DEh,03h,11111000b,00000010b ; p.mode 2
0
0DEh,03h,11000111b,00000000b ; Osc. enable
0FFh
0DEh,03h,11111000b,00000011b ; p.mode 3
0FEh
0FEh
0FEh
0FEh
0DEh,03h,11111111b,00011000b ; No decode,Osc. disable
0
0DEh,03h,11001111b,00000000b ; Osc. ena, normal clock
0FFh
0DEh,03h,11110000b,00001100b ; No decode,p.mode 4
0
X12-AN-003-02
; Delay
; Wait for Vsync
; Delay
; Delay
; Delay
; Wait for Vsync
; Wait for Vsync
; Wait for Vsync
; Wait for Vsync
; Delay
411-1.0
SPC8106