SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 414

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

The SDU8106B0F is assembled with one 5V, 256Kx16 configuration, symmetrical architecture (9
rows x 9 columns; 2 / CAS signals), SMD, SOJ package DRAM. For this design, MD6 input is left
open to support symmetrical architecture DRAM and MD10 input is left open to support 256 cycle
/ 32 ms refresh rate DRAM .
Configuration input MD7 selects the method for supporting a 16-bit LCD panel. The SPC8106 will
not support a CRT while directly supporting the 16-bit LCD panel using the internal interface. For
the purpose this design, MD7 is left open to support 16-bit LCD panel interface through an exter-
nal latch, thus at the same time providing full CRT support. See “SDU8106B0F Rev. 1.0 Sche-
matics (6 of 7)” on page 24 for further details.
The SPC8106 can either operate with 5.0V or 3.3V core operating voltage which is configurable
through MD8 input. For the purpose of this design, MD8 is set to logic low to support only 3.3V
VCC core operating voltage.
During Hardware Power Save Mode (and Power Save Mode 4), provision must be made to
refresh the video DRAM. As shown in the following table, there are four options. Option one uses
the frequency source connected to CLK1. Option two uses the ISA /REFRESH signal (which is
connected to SPC8106 pin MEMEN). Option three is for the case when the DRAM supports self-
refresh capability. Option four selects a 64 kHz signal connected to SPC8106 pin PDCLK. Self-
refresh DRAM is used for this design. Therefore, option three is used to refresh the video DRAM.
For this design, MD11 input is set to logic low and MD12, MD14 inputs are left open according to
the table below.)
The MD13 configuration input selects between external 32 kHz PD clock support and CRT spite
capabilities. The MD13 input is set to a logic low on power-up to select CRT spite capabilities. For
the purpose of this design, the external 32 kHz PD clock is not supported.
SDU8106B
EV2-12
MD6 and MD10 Video DRAM Configuration
MD7 16-Bit LCD Interface Support
MD8 Core Operating Voltage
MD11 - MD12 and MD14 Power Save Mode DRAM Refresh Source
MD13 Configuration Input
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
0F
0 = closed, 1 = open
MD1
Rev. 1.0 Evaluation Board User Manual
4
1
1
1
1
= hard-wired configuration
MD1
Table 0-5 SPC8106 Power Save Mode
2
0
0
1
1
DRAM Refresh Source Select
MD1
1
0
1
0
1
Option
1
2
3
5
CLK1
MEMEN (ISA /
REFRESH
Self Refresh DRAM
PDCLK (64 kHz)
Refresh Source
X12-AN-005-02
411-1.0
SPC8106