SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 132

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

bit 7
bit 6
bit 5
bit 4
bit 2
bit 1
bit 0
Hardware Functional Specification
SP1-90
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Mode Enable
AUX[00] bit 6
12-Bit RGB
0
1
RGBI Mode Enable
This bit enables an RGBI, 4-bit value to be directly driven out on the LD[3:0] pins at the pixel clock
rate. The RGBI value represents the EGA palette index. This bit, when asserted, alters the function
of the LCD interface. See “RGBI Mode Dual LCD Panel Timing” on page 70.
12-bit RGB Mode Enable
This bit enables a 12 bits per pixel, 4 bits per primary color to be directly driven on the LCD and
CRT overlay output pins at the pixel clock rate. The 12-bit value represents the output from the
internal look up table. See “12-bit RGB Mode LCD Panel Timing” on page 70. This bit must be set
to 1 for 12-bit TFT panel operation.
TFT Enable
This bit enables the TFT mode. When this bit = 1, it forces the LCD enable bit, AUX[0B] bit 0 to 1
enabling the LCD interface. This bit works in conjunction with the CRT enable bit as follows:
Test Mode Enable
The Test Mode Enable bit must be set to 0 for normal operation. When set to 1, the chip is placed
into device test mode and the test input and test output selector bits in Auxiliary Register 04h are
enabled.
IRQ Output Enable
When the IRQ Output Enable bit = 0, the IRQ output is held in a high impedance state. When this
bit = 1, the IRQ output pin is enabled and will be driven to indicate the Vertical Retrace interrupt
status.
Multi-Font Enable
When the Multi-Font Enable bit = 0, normal text mode font selection is enabled. When this bit = 1, it
allows bits 0 through 2 of the attribute byte (foreground color) to select one of eight simultaneously
displayable fonts. In this case the attribute byte foreground color bits (normally bits 0 to 2) are
forced to 1, the font selection bit (bit 3) is not used, and the blink/intensity bit (bit 7) functions nor-
mally.
LCD B Registers Program Enable
This bit is used to access the hidden Horizontal Panel Size and Vertical Panel Size registers (LCD
B Registers), which reside in the same address space as their CRT mode counterparts. These hid-
den timing registers only have an effect when the LCD is the active display. When this bit = 0,
accesses to CRTC Register [01] affect the normal Horizontal Total Register, and accesses to
CRTC Register [12] affect the normal Vertical Display Enable End Register. When this bit = 1, then
the “B-set” registers are accessible, and accesses to CRTC Register [01] affect the Horizontal
Panel Size Register, and accesses to CRTC Register [12] affect the Vertical Panel Size Register.
These “B-set” registers are used for LCD only mode (AUX[0B] bits 1,0 = 01). The Protect Registers
bit (CRTC[11] bit 7) has no effect when programming the CRTC “B-set” registers.
TFT Enable Bit
AUX[00] bit 5
0
1
1
Table 0-50 Display Enable Bits
CRT Enable Bit
AUX[0B] bit 1
X12-SP-001-07
0
1
0
1
0
1
LCD Enable Bit
AUX[0B] bit 0
X
X
X
X
0
1
0
1
LCD DoubleScan mode
12-bit TFT CRT mode /
9-bit TFT CRT mode /
12-bit TFT LCD mode
Standard LCD mode
9-bit TFT LCD mode
Display Mode
DoubleScan
DoubleScan
CRT mode
no display
411-1.0
SPC8106