SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 115

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

Options
Options
SPC8106
Software Power Save Mode 3
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Software Power Save Mode 4
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411-1.0
No video display accesses to display memory.
No CPU accesses to/from display memory.
Sequencer is halted.
No display memory refresh.
I/O read/write of all registers is allowed (except LUT and RAMDAC registers).
LCDPWR# and IREFEN# signals forced high.
LCD and TFT interface output signals tri-stated or forced low, depending on the state of the LCD Signal PS
Mode bit in LCD Support Register 1, AUX[02] bit 1.
If CRT display enabled, CRT and RAMDAC interface signals forced low (except DACRD# and DACWR#
which are forced high).
I/O read/write to all registers except Auxiliary Registers can be disabled.
The active internal clock oscillator cell can be disabled if a 2-terminal crystal is used. Note that the non-
selected internal clock oscillator is automatically disabled in all active and power-save modes.
No video display accesses to display memory.
No CPU accesses to/from display memory.
Sequencer is halted.
Display memory refresh is maintained and is generated from one of 3 selectable sources: 1) from the active
CLKI input (28 MHz for LCD, 25 MHz or 28 MHz for CRT), 2) from the PDCLK pin (32 kHz 50% duty cycle, or
64 kHz with short high pulse duration), 3) or from a clock source connected to pin MEMEN.
Refresh rate generated from CLKI can be selected: 64 kHz or 8 kHz, (for 256 cycle/4 ms, or 256 cycle/32 ms
DRAM, respectively).
Refresh rate generated from MEMEN or PDCLK can also be selected: 64 kHz or 8 kHz, (for 256 cycle/4 ms,
or 256 cycle/32 ms DRAM, respectively).
I/O read/write of all registers is allowed (except LUT and RAMDAC registers).
LCDPWR# and IREFEN# signals forced high.
LCD and TFT interface output signals tri-stated or forced low, depending on the state of the LCD Signal PS
Mode bit in LCD Support Register 1, AUX[02] bit 1.
If CRT display enabled, CRT and RAMDAC interface signals forced low (except DACRD# and DACWR#
which are forced high).
I/O read/write to all registers except Auxiliary Registers can be disabled.
Select MEMEN input pin, PDCLK input pin, or internally divided down CLKI as the clock source for display
memory refresh generation.
Select self-refresh mode, for DRAMs that support self-refresh.
The active internal clock oscillator cell can be disabled if a 2-terminal crystal is used. Note that the non-
selected internal clock oscillator is automatically disabled in all active and power-save modes.
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
X12-SP-001-07
Hardware Functional Specification
SP1-73