MT57W1MH18C Micron Semiconductor Products, Inc., MT57W1MH18C Datasheet - Page 9

• Manufacturer Part Number: MT57W1MH18C
• Description: 18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 5:
18Mb: 2 Meg x 8, 1 Meg x 18, 512K x 36, 1.8V V
MT57W1MH18C_H.fm – Rev. H, Pub. 3/03
SYMBOL
CQ#, CQ
NW_#
BW_#
V
R/W#
DLL#
TMS
TDO
V
LD#
TCK
V
TDI
D_
K#
SA
ZQ
Q_
DD
C#
C
K
REF
DD
Q
Output
Output
Output
Supply
Supply
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Ball Descriptions
DESCRIPTION
Synchronous Byte Writes (or Nibble Writes on x8): When LOW, these inputs cause their respective
bytes to be registered and written if W# had initiated a WRITE cycle. These signals must meet setup
and hold times around the rising edges of K and K# for each of the two rising edges comprising the
WRITE cycle. See Ball Layout figures for signal to data relationships.
Output Clock: This clock pair provides a user-controlled means of tuning device output data. The
rising edge of C# is used as the output timing reference for first output data. The rising edge of C is
used as the output reference for second output data. Ideally, C# is 180 degrees out of phase with C.
C and C# may be tied HIGH to force the use of K and K# as the output reference clocks instead of
having to provide C and C# clocks. If tied HIGH, these inputs may not be allowed to toggle during
device operation.
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See Ball Layout figures for ball site location of individual signals.
The x8 device uses D0:D7. Remaining signals are NC. The x18 device uses D0:D17. Remaining signals
are NC. The x36 device uses D0:D35. Remaining signals are NC.
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable, low-frequency
operation.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and read/write direction. All transactions operate on a burst of two data
(one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when
R/W# is HIGH, WRITE when R/W# is LOW) for the loaded address. R/W# must meet the setup and
hold times around the rising edge of K.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. See Ball Layout figures for address expansion inputs. All transactions
operate on a burst of two words (one clock period of bus activity). These inputs are ignored when
both ports are deselected.
IEEE 1149.1 Clock Input: 1.8V I/O levels. This ball must be tied to V
in the circuit.
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is
not used in the circuit.
HSTL Input Reference Voltage: Nominally V
margin. Provides a reference voltage for the HSTL input buffer trip point.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball to
ground. Alternately, this ball can be connected directly to V
mode. This ball cannot be connected directly to GND or left unconnected.
Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as data valid indication. These signals run freely and do
not stop when Q tri-states.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K#
rising edges if C and C# are tied HIGH. This bus operates in response to R# commands. See Ball
Layout figures for ball site location of individual signals. The x8 device uses Q0:Q7. Remaining
signals are NC. The x18 device uses Q0:Q17. Remaining signals are NC. The x36 device uses Q0:Q35.
Remaining signals are NC.
IEEE 1149.1 Test Output: 1.8V I/O level.
Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions for range.
Power Supply: Isolated Output Buffer Supply: Nominally, 1.5V. 1.8V is also permissible. See DC
Electrical Characteristics and Operating Conditions for range.
DD
, HSTL, DDR SIO SRAM
9
2 MEG
DD
1.8V V
Q/2 but may be adjusted to improve system noise
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
8, 1 MEG
DD
DD
, HSTL, DDR SIO SRAM
Q to enable the minimum impedance
SS
if the JTAG function is not used
X
18, 512K
©2003 Micron Technology, Inc.
X
36