MT57W1MH18C Micron Semiconductor Products, Inc., MT57W1MH18C Datasheet - Page 5

• Manufacturer Part Number: MT57W1MH18C
• Description: 18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

NOTE:
18Mb: 2 Meg x 8, 1 Meg x 18, 512K x 36, 1.8V V
MT57W1MH18C_H.fm – Rev. H, Pub. 3/03
1. In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets setup
2. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
3. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
4. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
MASTER
ASIC)
and hold times at the bus master.
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
BUS
(CPU
or
SRAM 1 Input CQ#
SRAM 4 Input CQ#
SRAM 1 Input CQ
SRAM 4 Input CQ
Delayed K#
DATA OUT
Delayed K
Source K#
Source K
DATA IN
Address
R/W#
BW#
LD#
DD
Vt
, HSTL, DDR SIO SRAM
R
R
R = 50Ω
D
SA
Figure 3: Application Example
LD
Vt = V
LD
#
#
R/W
R/W
#
#
SRAM 1
REF
W
W
B
#
B
#
C C#
K
CQ#
5
ZQ
CQ
K#
Q
2 MEG
R = 250Ω
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
8, 1 MEG
DD
, HSTL, DDR SIO SRAM
D
SA
R
Vt
Vt
LD
#
X
R/W
SRAM 2
#
18, 512K
W
B
#
C C#
©2003 Micron Technology, Inc.
K
CQ#
CQ
ZQ
K#
Q
X
R = 250Ω
36