MT57W1MH18C Micron Semiconductor Products, Inc., MT57W1MH18C Datasheet

MT57W1MH18C

Manufacturer Part Number

MT57W1MH18C

Description

18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT57W1MH18C.pdf (28 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

MT57W1MH18CF-4

Manufacturer:

MICRON/美光

Quantity:

20 000

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18Mb DDR SIO SRAM

2-WORD BURST

Features

• DLL circuitry for accurate output data placement

• Separate independent read and write data ports

• DDR READ or WRITE operation initiated each cycle

• Fast clock to valid data times

• Full data coherency, providing most current data

• Two-tick burst counter for low DDR transaction size

• Double data rate operation on read and write ports

• Two input clocks (K and K#) for precise DDR timing

• Two output clocks (C and C#) for precise flight time

• Optional-use echo clocks (CQ and CQ#) for flexible

• Single address bus

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• Core V

• Clock-stop capability with µs restart

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

• User-programmable impedance output

• JTAG boundary scan

NOTE:

18Mb: 2 Meg x 8, 1 Meg x 18, 512K x 36, 1.8V V

MT57W1MH18C_H.fm – Rev. H, Pub. 3/03

Options

• Clock Cycle Timing

• Configurations

• Package

• Operating Temperature Range

1. A Part Marking Guide for the FBGA devices can be found on

at clock rising edges only

and clock skew matching—clock and data delivered

together to receiving device

receive data synchronization

(±0.1V) HSTL

package

Micron’s Web

3ns (333 MHz)

3.3ns (300 MHz)

4ns (250 MHz)

5ns (200 MHz)

6ns (167 MHz)

7.5ns (133 MHz)

2 Meg x 8

1 Meg x 18

165-ball, 13mm x 15mm FBGA

Commercial (0°C £ T

512K x 36

= 1.8V (±0.1V); I/O V

site—http://www.micron.com/numberguide.

£ +70°C)

, HSTL, DDR SIO SRAM

Q = 1.5V to V

MT57W1MH18C

MT57W512H36C

MT57W2MH8C

Marking

None

-3.3

-7.5

-3

-4

-5

-6

2 MEG

Table 1:

General Description

lined burst SRAM employs high-speed, low-power

CMOS designs using an advanced 6T CMOS process.

(double data rate) ports to access the memory array.

The read port has dedicated data outputs to support

READ operations. The write port has dedicated data

inputs to support WRITE operations. This architecture

eliminates the need for high-speed bus turnaround.

Access to each port is accomplished using a common

address bus. Addresses for reads and writes are latched

on the rising edge of the K input clock. Each address

location is associated with two words that burst

sequentially into or out of the device. Bus turnaround

cycles are eliminated and a new data transaction can

be requested each clock cycle, permitting higher

request rates than DDR SRAMs without separated

input and output buses.

MT57W2MH8C

MT57W1MH18C

MT57W512H36C

PART NUMBER

MT57W2MH8CF-xx

MT57W1MH18CF-xx

MT57W512H36CF-xx

The Micron

The DDR architecture consists of two separate DDR

1.8V V

Figure 1: 165-Ball FBGA

8, 1 MEG

Valid Part Numbers

DDR separate I/O, synchronous, pipe-

, HSTL, DDR SIO SRAM

DESCRIPTION

2 Meg x 8, DDR SIOb2 FBGA

1 Meg x 18, DDR SIOb2 FBGA

512K x 36, DDR SIOb2 FBGA

18, 512K

Related parts for MT57W1MH18C

MT57W1MH18C Summary of contents

Page 1

... A NOTE Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/numberguide. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V MT57W2MH8C MT57W1MH18C MT57W512H36C Table 1: ...

Page 2

... This permits any random operation without ever needing bus turnaround delays. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V READ cycles are pipelined. The request is initiated by driving R/W# HIGH and providing the address at K rising edge ...

Page 3

... It can be placed into a stopped-clock state to minimize power, with a 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V modest restart time of 1,024 clock cycles. Circuitry automatically resets the DLL when the absence of an input clock is detected ...

Page 4

... For 1 Meg 18; BWx separate byte writes. For 512K 36; BWx separate byte writes. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 2: Functional Block Diagram 2 Meg Meg x 18; 512K x 36 ...

Page 5

... For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 3: Application Example R = 250Ω ...

Page 6

... Expansion address: 2A for 72Mb 2. NW1# controls writes to D4:D7 3. Expansion address: 7A for 144Mb 4. Expansion address: 10A for 36Mb 5. Expansion address: 5B for 288Mb 6. NW0# controls writes to D0:D3 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1. ...

Page 7

... Expansion address: 2A for 144Mb 2. Expansion address: 3A for 36Mb 3. BW1# controls writes to D9:D17 4. Expansion address: 7A for 288Mb 5. Expansion address: 10A for 72Mb 6. BW0# controls writes to D0:D8 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1. ...

Page 8

... BW2# controls writes to D18:D26 4. BW1# controls writes to D9:D17 5. Expansion address: 9A for 36Mb 6. Expansion address: 10A for 144Mb 7. BW3# controls writes to D27:D35 8. BW0# controls writes to D0:D8 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1. ...

Page 9

... Power Supply: Isolated Output Buffer Supply: Nominally, 1.5V. 1.8V is also permissible. See DC DD Electrical Characteristics and Operating Conditions for range. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, DDR SIO SRAM ...

Page 10

... No Connect: These balls are internally connected to the die, but have no function and may be left not connected to the board to minimize ball count. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X X 1.8V V ...

Page 11

... State transitions (LD# = LOW (LD# = HIGH (R/W# = HIGH (R/W# = LOW). 3. State machine, control timing sequence is controlled by K. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 4: Bus Cycle State Diagram L READ DOUBLE ...

Page 12

... This table illustrates the operation for the x18 devices. The x36 device operation is similar, except for the addition of BW2# (controls D18:D26) and BW3# (controls D27:D35). The x8 device operation is similar, except that NW0# controls D0:D3, and NW1# controls D4:D7. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. ...

Page 13

... Input High (Logic 1) Voltage Input Low (Logic 0) Voltage 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional ...

Page 14

... Table 12: Thermal Resistance Note 13; notes appear following parameter tables on page 17 DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Balls (Bottom) 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V £ +70° SYM TYP -3 ³ ...

Page 15

... X t CQ, CQ# HIGH CQHQ 0.25 to output valid V t CQ, CQ# HIGH CQHQ -0.25 to output hold X C HIGH to t CHQZ 0.45 output High-Z 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V -3.3 -4 MIN MAX MIN MAX MIN 3.47 3.30 4.20 4.00 5.25 5.00 0.20 0.20 1.32 1.60 2.00 1.32 1 ...

Page 16

... Hold Times K rising edge t 0.40 KHAX to address hold 0.40 K rising edge t KHIX to control inputs hold 0. rising t KHDX edge to data-in hold 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1. MIN MAX MIN MAX MIN MAX -0.45 -0.45 -0.45 0.40 0.50 0.60 0.40 0.50 0.60 ...

Page 17

... NOP currents are valid when entering NOP after all pending READ and WRITE cycles are com- pleted. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1. 12. Average I/O current and power is provided for OH informational purposes only and is not tested ...

Page 18

... V ZQ for 50 W impedance 250 W Output load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 5 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDR SIO SRAM ...

Page 19

... Outputs are disabled (High-Z) one clock cycle after a NOP this example, if address A3 = A4, then data Q40 = D30 and Q42 = D31. Write data is forwarded immediately as read results. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 6: READ/WRITE Timing READ ...

Page 20

... The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. ...

Page 21

... SRAM with mini- mal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is executed. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDR SIO SRAM ...

Page 22

... TDI and TDO balls when the TAP controller Shift-DR state. It also places all SRAM outputs into a High-Z state. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, DDR SIO SRAM ...

Page 23

... CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG X 1.8V V Figure 9: TAP Timing ...

Page 24

... This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have the DC values as defined in Table 8, ”DC Electrical Characteristics and Operating Conditions,” on page 13. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1. 1.8V TAP AC Output Load Equivalent ...

Page 25

... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V ALL DEVICES DESCRIPTION 000 Revision number. 00def0wx0t0q0b0s0 ...

Page 26

... Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, DDR SIO SRAM DD BIT# FBGA BALL 37 10D 10C 40 11D ...

Page 27

... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of of Micron Technology, Inc. 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub 3/03 2 MEG 1.8V V Figure 11: 165-Ball FBGA ...

Page 28

... Changed AC timing Rev. 2, Pub. 11/01, ADVANCE .......................................................................................................................................11/01 • New ADVANCE data sheet 18Mb: 2 Meg Meg x 18, 512K x 36, 1. HSTL, DDR SIO SRAM DD MT57W1MH18C_H.fm – Rev. H, Pub. 3/03 2 MEG X 1.8V V test conditions for read to write ratio DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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