MT54V1MH18A Micron Semiconductor Products, Inc., MT54V1MH18A Datasheet

MT54V1MH18A

Manufacturer Part Number

MT54V1MH18A

Description

18Mb QDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT54V1MH18A.pdf (25 pages)

Current page: 1 of 25
Download datasheet (376Kb)

18Mb QDR

2-WORD BURST

Features

• Separate independent read and write data ports

• 100 percent bus utilization DDR READ and WRITE

• High frequency operation with future migration to

• Fast clock to valid data times

• Full data coherency, providing most current data

• Two-tick burst counter for low DDR transaction size

• Double data rate operation on read and write ports

• Two input clocks (K and K#) for precise DDR timing

• Two output clocks (C and C#) for precise flight time

• Optional-use echo clocks (CQ and CQ#) for flexible

• Single address bus

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• 2.5V core and 1.5 to 1.8V (±0.1V) HSTL I/O

• Clock-stop capability

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

• User-programmable impedance output

• JTAG boundary scan

NOTE:

18Mb: 2.5V V

MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03

Options

• Clock Cycle Timing

• Configurations

• Package

• Operating Temperature Range

1. A Part Marking Guide for the FBGA devices can be found on

with concurrent transactions

operation

higher clock frequencies

at clock rising edges only

and clock skew matching—clock and data delivered

together to receiving device

receive data synchronization

package

Micron’s Web site—http://www.micron.com/numberguide.

6ns (167 MHz)

7.5ns (133 MHz)

10ns (100 MHz)

1 Meg x 18

165-ball, 13mm x 15mm FBGA

Commercial (0°C £ T

512K x 36

, HSTL, QDRb2 SRAM

£ +70°C)

™

SRAM

MT54V512H36A

MT54V1MH18A

Marking

None

-7.5

-10

-6

Table 1:

General Description

nous, pipelined burst SRAM employs high-speed, low-

power CMOS designs using an advanced 6T CMOS

process.

(double data rate) ports to access the memory array.

The read port has dedicated data outputs to support

READ operations. The write port has dedicated data

inputs to support WRITE operations. This architecture

eliminates the need for high-speed bus turnaround.

Access to each port is accomplished using a common

address bus. Addresses for reads and writes are latched

on rising edges of the K and K# input clocks, respec-

tively. Each address location is associated with two

words that burst sequentially into or out of the device.

Since data can be transferred into and out of the device

on every rising edge of both clocks (K and K# and C

and C#), memory bandwidth is maximized and system

design is simplified by eliminating bus turnarounds.

MT54V1MH18A

MT54V512H36A

PART NUMBER

MT54V1MH18AF-xx

MT54V512H36AF-xx

The Micron

The QDR architecture consists of two separate DDR

2.5V V

Figure 1: 165-Ball FBGA

Valid Part Numbers

1 MEG x 18, 512K x 36

QDR™ (Quad Data Rate™) synchro-

, HSTL, QDRb2 SRAM

DESCRIPTION

1 Meg x 18, QDRb2 FBGA

512K x 36, QDRb2 FBGA

Related parts for MT54V1MH18A

Related keywords

MT54V1MH18A datasheet
MT54V1MH18A data sheet
MT54V1MH18A pdf datasheet
MT54V1MH18A component
MT54V1MH18A part
MT54V1MH18A distributor
MT54V1MH18A RoHS
MT54V1MH18A datasheet download