MT57W1MH18C Micron Semiconductor Products, Inc., MT57W1MH18C Datasheet - Page 2

• Manufacturer Part Number: MT57W1MH18C
• Description: 18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

device select (LD#), which is received at K rising edge.
All synchronous inputs pass through registers con-
trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte write or nibble
write selection. Write data and byte writes are regis-
tered on the rising edges of both K and K#. The
addressing within each burst of two is fixed and
sequential, beginning with the lowest address and
ending with the highest address. All synchronous data
outputs pass through output registers controlled by
the rising edges of the output clocks (C and C# if pro-
vided, otherwise K, K#).
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that require a
new transaction to be initiated each clock cycle.
sramds) for the latest data sheet.
READ/WRITE Operations
burst-of-two data and require one full clock cycle of
bus utilization. Any transaction type can be initiated at
K rising edge independent of the previous transaction
type. This permits any random operation without ever
needing bus turnaround delays.
18Mb: 2 Meg x 8, 1 Meg x 18, 512K x 36, 1.8V V
MT57W1MH18C_H.fm – Rev. H, Pub. 3/03
Depth expansion is accomplished with a single
Four balls are used to implement JTAG test capabili-
The SRAM operates from a 1.8V power supply, and
Please refer to Micron’s Web site
All bus transactions operate on an uninterruptable
DD
, HSTL, DDR SIO SRAM
(www.micron.com/
2
2 MEG
by driving R/W# HIGH and providing the address at K
rising edge. Data is delivered after the next rising edge
of K# (t + 1), using C and C# as the output timing refer-
ences; or K and K# if C and C# are tied HIGH. If C and
C# are tied HIGH, they may not be toggled during
device operation. Output tri-stating is automatically
controlled so that the bus is released if no data is being
delivered. This permits banked SRAM systems with no
complex output enable (OE) timing generation. Back-
to-back READ cycles can be initiated at every K rising
edge.
and providing the address at K rising edge. Data is
expected at the rising edge of K and K#, beginning at
the next K rising edge after the cycle is initiated. Write
registers are incorporated to facilitate pipelined self-
timed WRITE cycles and to provide fully coherent data
for all combinations of reads and writes. A read can
immediately follow a write even if they are to the same
address. Although the write data has not been written
to the memory array, the SRAM will deliver the data
from the write register instead of using the older data
from the memory array. The latest data is always uti-
lized for all bus transactions. WRITE cycles can be ini-
tiated on every K rising edge.
PARTIAL WRITE Operations
x8 devices in which nibble write is supported. The
active LOW byte write controls, BWx# (NWx#), are reg-
istered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
READ cycles are pipelined. The request is initiated
WRITE cycles are initiated by driving R/W# LOW
BYTE WRITE operations are supported, except for
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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8, 1 MEG
DD
, HSTL, DDR SIO SRAM
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18, 512K
©2003 Micron Technology, Inc.
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36