MT28C6428P20 Micron Semiconductor Products, Inc., MT28C6428P20 Datasheet
MT28C6428P20
Related parts for MT28C6428P20
MT28C6428P20 Summary of contents
Page 1
... ERASE-SUSPEND-to-PROGRAM within same bank • Read/Write SRAM during program/erase of Flash 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S ...
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... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY fied as low as 1.0V. The MT28C6428P20 and MT28C6428P18 devices support two F_V ranges, an in-circuit voltage of 0.9V–2.2V and a produc- tion compatibility voltage of 12V ±5%. The 12V ±5% ...
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... NOTE: 1. For part number combinations not listed in this table, please contact your Micron representative. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Valid combinations of features and their correspond- ing part numbers are listed in Table 2 ...
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... F_WE# F_OE# WSM I/O Logic Address Input A0–A21 Buffer Address Latch 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BLOCK DIAGRAM F_V F_V CC PP Bank a FLASH 4,096K x 16 ...
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... Output C8, B10, F8, F7, E8, E6, D7, C7, B9 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0– ...
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... H12 C6, D5, D6, – E7 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Flash Program/Erase Power Supply: [0.9V–2.2V or 11.4V–12.6V]. Operates as input at logic levels to control complete device protection. Provides backward compatibility for factory programming when driven to 11.4V– ...
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... Data output on upper byte only; lower byte High-Z. 9. Data input on lower byte only. 10. Data input on upper byte only. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY SRAM SIGNALS ...
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... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Figure 2 Bottom Boot Block Device Bank b = 48Mb Block Block Size Address Range (K-bytes/ ...
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... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Figure 3 Top Boot Block Device Bank b = 48Mb Block Block Size Address Range (K-bytes/ ...
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... I/O pins DQ0–DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0–DQ7 (see Table 8). 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY COMMAND DEFINITION ...
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... WD: Data to be written at the location WA X: “Don’t Care” 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 3. The 8-bit command code is input to the device on DQ0– ...
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... Program Device First Protection Register Lock Device First Protection Register 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table 5 Command Descriptions DESCRIPTION Prepares for an accelerated program operation. ...
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... Invalid/Reserved D1h Check Block Second Erase Confirm 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table 5 DESCRIPTION If the previous command was an ERASE SETUP command, then the CSM closes the address and data latches, and it begins erasing the block indicated on the address pins ...
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... DQ0–DQ7 to the bank containing address 00h and the identification code address on the address 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY lines. Control signals F_CE# and F_OE# must ...
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... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table ...
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... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table ...
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... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table ...
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... MODE Read (array, status registers, device identification register, or query) Standby Output Disable Reset Write 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table ...
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... For in-factory programming, the APA, along with an optimized set of programming parameters, minimizes chip programming time when 11.4V ≤ F_V 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY For in-system programming, when 0.9V ≤ F_V 2 ...
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... SR0 RESERVED FOR FUTURE ENHANCEMENT 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY CHECK BLOCK ERASE and the second one to start the execution of the command. If after the operation the ...
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... SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS ...
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... Command NO Finished Reading ? YES Issue PROGRAM RESUME Command PROGRAM Resumed 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND COMMENTS WRITE READ Standby Standby WRITE ...
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... Word Address Issue 32 sequences of Word Address and Word Data SR7 = 0? YES PROGRAM Complete 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND WRITE WRITE NO ...
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... SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS ...
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... ERASE Continued NOTE: 1. See Word Programming Flowchart for complete programming procedure. 2. See BLOCK ERASE Flowchart for complete erasure procedure. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS ...
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... Block Address NO SR7 = 1? YES NO SR5 = 0? YES BLOCK ERASE Complete 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND COMMENTS WRITE WRITE READ Standby Error Micron Technology, Inc ...
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... For a top boot device, reading of the CFI table or the chip protection register is only allowed if bank read array mode. BLOCK LOCKING The Flash memory of the MT28C6428P20 and MT28C6428P18 devices provide a flexible locking scheme which allows each block to be individually locked or unlocked with no latency. ...
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... It can only be cleared by reset or power- down, not by software. Table 9 shows the block locking state transition scheme. The READ ARRAY command, 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table 9 ...
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... NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. “XX” specifies the block address of lock configuration. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Protection Register Memory Map ...
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... Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY A factory option provides in-system programming ...
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... V Q/2. Input rise and fall times (10% to 90%) < 5ns Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to PP the device ...
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... Any read operation performed while in suspend mode will add a current draw Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY 1 F_V CONDITIONS SYMBOL ...
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... Any read operation performed while in suspend mode will add a current draw Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY 1 (continued) F_V CONDITIONS ...
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... F_RP# HIGH to output delay CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change READ cycle time RST# deep power-down 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY SYMBOL C -80 – ...
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... Program suspend latency Erase suspend latency Chip programming time 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY -80 – F_V = 1 ...
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... NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY VALID ADDRESS ...
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... MIN ACE 80 t AOE 25 t RWH 200 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY VALID ADDRESS ACE t RWH -85 = 1.70V–1.90V MAX ...
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... MIN ACE 80 t APA 30 t AOE 25 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY VALID ADDRESS VALID VALID ADDRESS ADDRESS ACE t AOE VALID ...
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... SYMBOL MIN MAX MIN t RWH 200 t RP 100 100 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY RESET OPERATION t RP -85 = 1.70V–1.90V MAX UNITS 250 ns ns ...
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... Top boot block device ……96KB blocks of 5F00, 0001 Bottom boot block device ……96KB blocks of 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table 12 CFI ...
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... SRAM density, 8Mb (512K x 16) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Table 12 CFI (continued) DESCRIPTION n user programmable bytes Micron Technology, Inc ...
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... S_CE1# S_CE2 S_WE# S_OE# S_UB# S_LB# 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY S_OE addresses A0–A3. S_UB# and S_LB# control the data width as described above ...
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... Write recovery time Write to High-Z output Data to write time overlap Data hold from write time End write to Low-Z output 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY to 0.9V S_V CC CC ...
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... LB Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY READ CYCLE 1 ; S_CE2, S_WE PREVIOUS DATA VALID READ CYCLE 2 ...
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... LBW UBW Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY WRITE CYCLE (S_WE# CONTROL LBW, t UBW High-Z t WHZ -85 = 1.70V– ...
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... LBW UBW Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY WRITE CYCLE 2 (S_CE1# CONTROL LBW, t UBW WHZ -85 = 1.70V– ...
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... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY 67-BALL FBGA 8 ...
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... Updated the block locking information Initial published release, ADVANCE, Rev. 1 ............................................................................................................... 1/02 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. ...