MT28C3214P2 Micron Semiconductor Products, Inc., MT28C3214P2 Datasheet
MT28C3214P2
Related parts for MT28C3214P2
MT28C3214P2 Summary of contents
Page 1
... Dual 64-bit chip protection registers for security purposes • PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256K x 16 SRAM COMBO MEMORY MT28C3214P2FL MT28C3214P2NFL ...
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... MT28C3214P2FL-11 BET MT28C3214P2FL-11 TET MT28C3214P2NFL-11 TET 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY The MT28C3214P2FL and MT28C3214P2NFL de- vices contain an asynchronous 4Mb SRAM organized as 256K-words by 16 bits. These devices are fabricated using an advanced CMOS process and high-speed/ ultra-low-power circuit technology ...
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... MT28C3214P2FL-10 TET MT28C3214P2FL-11 BET MT28C3214P2FL-11 TET MT28C3214P2NFL-11 TET 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY Valid combinations of features and their correspond- ing part numbers are listed in Table 3. Figure 1 Part Number Chart ...
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... F_CE# CSM F_WE# F_OE# WSM I/O Logic Address Input A0–A20 Buffer Address Latch 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY BLOCK DIAGRAM F_V F_V CC PP Bank a FLASH 2,048K x 16 Bank b SRAM ...
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... C10, D7, E6, E8, E9, E10, F7, F8, F9, F10 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0– ...
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... A12, C4, H1, H2, H10, H11, H12 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY Flash Program/Erase Power Supply: [0.9V–2.2V or 11.4V–12.6V]. Operates as input at logic levels to control complete device protection. Provides backward compatibility for factory programming when driven to 11.4V– ...
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... Data output on upper byte only; lower byte High-Z. 9. Data input on lower byte only. 10. Data input on upper byte only. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY SRAM SIGNALS H SRAM must be High-Z ...
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... Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY Figure 2 Bottom Boot Block Device Address Range Block (x16) (K-bytes/K-words) 1F8000h-1FFFFFh 14 1F0000h-1F7FFFh 13 1E8000h-1EFFFFh 12 1E0000h-1E7FFFh 11 1D8000h-1DFFFFh 10 1D0000h-1D7FFFh 9 1C8000h-1CFFFFh ...
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... Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY Figure 3 Top Boot Block Device Address Range Block (x16) (K-bytes/K-words) 1FF000h-1FFFFFh 55 1FE000h-1FEFFFh 54 1FD000h-1FDFFFh 53 1FC000h-1FCFFFh 52 1FB000h-1FBFFFh 51 1FA000h-1FAFFFh 50 1F9000h-1F9FFFh ...
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... B0h C0h D0h FFh 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY logic LOW level (V logic HIGH (V Table 7 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. ...
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... PA: Protection register address 10. LPA: Lock protection register address 11. PD: Protection register data 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 4. The 8-bit command code is input to the device on DQ0– ...
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... First Protection Register Lock Device First Protection register 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY Table 6 Command Descriptions DESCRIPTION Operates the same as a PROGRAM SETUP command. ...
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... D0h Unlock Block Second 00h Invalid/Reserved 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY Table 6 DESCRIPTION If the previous command was an ERASE SETUP command, then the CSM closes the address and data latches, and it begins erasing the block indicated on the address pins ...
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... DQ0–DQ7 to the bank containing address 00h 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY and the identification code address on the address lines ...
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... Standby Output Disable Reset Write 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY plished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid ad- dress within that block ...
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... V also checked before the PROGRAM/ERASE operation is verified by the WSM. The MT28C3214P2NFL device allows PROGRAM or ERASE at 0V, in which case SR3 is held at “0.” When PROGRAM SUSPEND is issued, WSM halts execution and sets both WSM and PSS bits to “ ...
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... SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY BUS ...
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... Issue READ ARRAY Command NO Finished Reading ? YES Issue PROGRAM RESUME Command PROGRAM Resumed 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND COMMENTS WRITE READ Standby Standby WRITE READ WRITE ...
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... SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY BUS ...
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... ERASE Continued NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure. 2. See Word Programming Flowchart for complete programming procedure. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY BUS OPERATION COMMAND COMMENTS ...
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... MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY BLOCK LOCKING The Flash memory of the MT28C3214P2FL or MT28C3214P2NFL device provides a flexible locking scheme which allows each block to be individually locked or unlocked with no latency. The device offers two-level protection for the blocks. ...
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... NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. “XX” specifies the block address of lock configuration. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY Table 9 Block Locking State Transition ...
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... A 128-bit protection register can be used to fullfill the security considerations in the system (preventing device substitution). 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY The 128-bit security area is divided into two 64-bit segments ...
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... This mode is entered auto- matically if no addresses or control signals toggle PROGRAM AND ERASE PP CC VOLTAGES The MT28C3214P2FL Flash memory provides in- system programming and erase with V 2.2V range ( addition to the flexible block lock ing, the V programming voltage can be held LOW for ...
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... PP 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to PP the device ...
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... This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY ...
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... This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY 1 ...
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... F_RP# HIGH to output delay F_RP# LOW pulse width CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change READ cycle time 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY -10 – ...
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... Word program time 4KW parameter block erase time 32KW parameter block erase time Program suspend latency Erase suspend latency 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY V = 1.65V CC 1.80V– ...
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... DH 0 NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY VALID ADDRESS VALID ADDRESS t AS ...
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... AOE 30 t RWH 200 100 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY VALID ADDRESS ACE t RWH READ TIMING PARAMETERS (V = 1.80V–2.20V) CC -11 = 1.65V–1.95V ...
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... APA 35 t AOE 30 t RWH 200 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY VALID ADDRESS VALID VALID ADDRESS ADDRESS ACE t AOE VALID High-Z OUTPUT t RMH ...
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... CC CC SYMBOL MIN MAX t RWH 200 t RP 125 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY RESET OPERATION t RP READ TIMING PARAMETERS (V = 1.80V–2.20V) CC -11 = 1.65V–1.95V MIN MAX ...
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... Top boot block device 56 blocks of 0037, 0000 Bottom boot block device 56 blocks of 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY Table 12 CFI DESCRIPTION n ms, 0000 = not supported ...
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... SRAM density, 4Mb (256K x 16) 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY Table 12 CFI (continued) DESCRIPTION n user programmable bytes Micron Technology, Inc ...
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... A4–A17 S_CE1# S_CE2 S_WE# S_OE# S_UB# S_LB# 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY S_OE addresses A0-A3. S_UB# and S_LB# control the data width as described above When in this SRAM WRITE ARRAY ...
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... Write pulse width Write recovery time Write to High-Z output Data to write time overlap Data hold from write time End write to Low-Z output 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY to 0. ...
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... CO 100 LB, UB 100 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY READ CYCLE 1 ; S_CE2, S_WE PREVIOUS DATA VALID READ CYCLE 2 (S_WE ...
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... LBW, UBW 100 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY WRITE CYCLE (S_WE# CONTROL LBW, t UBW High-Z t WHZ = 1.80V–2.20V ...
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... LBW, UBW 100 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY WRITE CYCLE 2 (S_CE1# CONTROL LBW, t UBW WHZ = 1.80V–2.20V ...
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... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 256K x 16 SRAM COMBO MEMORY 66-BALL FBGA 8 ...
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... Added second V range CC Initial published release, Rev. 1, Advance ................................................................................................................ 11/00 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY ) OH Micron Technology, Inc., reserves the right to change products or specifications without notice. ...