MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 9

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Paragraph
9.1
9.2
9.2.1
9.2.1.1
9.2.1.2
9.2.1.3
9.2.2
9.3
9.3.1
9.3.1.1
9.3.1.2
9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.3.3
9.3.4
9.3.5
9.3.5.1
9.3.5.2
9.3.5.3
9.3.5.4
9.3.6
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
9.4.2
9.4.3
9.4.3.1
9.4.3.2
9.4.3.3
9.4.3.4
9.4.3.5
9.4.3.6
9.4.3.7
9.4.3.8
9.4.3.9
9.5
MC68336/376
USER’S MANUAL
General ...................................................................................................... 9-1
QSM Registers and Address Map ............................................................. 9-2
Queued Serial Peripheral Interface ........................................................... 9-5
Serial Communication Interface .............................................................. 9-21
QSM Initialization .................................................................................... 9-30
QSM Global Registers ....................................................................... 9-2
QSM Pin Control Registers ............................................................... 9-4
QSPI Registers .................................................................................. 9-6
QSPI RAM ......................................................................................... 9-7
QSPI Pins .......................................................................................... 9-8
QSPI Operation ................................................................................. 9-8
QSPI Operating Modes ..................................................................... 9-9
Peripheral Chip Selects ................................................................... 9-20
SCI Registers .................................................................................. 9-21
SCI Pins .......................................................................................... 9-24
SCI Operation .................................................................................. 9-24
SECTION 10 CONFIGURABLE TIMER MODULE 4
Low-Power Stop Operation ....................................................... 9-2
Freeze Operation ...................................................................... 9-3
QSM Interrupts .......................................................................... 9-3
Control Registers ...................................................................... 9-6
Status Register .......................................................................... 9-7
Receive RAM ............................................................................ 9-7
Transmit RAM ........................................................................... 9-7
Command RAM ......................................................................... 9-8
Master Mode ........................................................................... 9-16
Master Wrap-Around Mode ..................................................... 9-19
Slave Mode ............................................................................. 9-19
Slave Wrap-Around Mode ....................................................... 9-20
Control Registers .................................................................... 9-21
Status Register ........................................................................ 9-24
Data Register .......................................................................... 9-24
Definition of Terms .................................................................. 9-25
Serial Formats ......................................................................... 9-25
Baud Clock .............................................................................. 9-25
Parity Checking ....................................................................... 9-26
Transmitter Operation ............................................................. 9-26
Receiver Operation ................................................................. 9-28
Idle-Line Detection .................................................................. 9-28
Receiver Wake-Up .................................................................. 9-29
Internal Loop ........................................................................... 9-30
TABLE OF CONTENTS
(Continued)
Title
MOTOROLA
Page
ix