MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 132

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

5.8.5 Interrupt Acknowledge Bus Cycles
5.9 Chip-Selects
5-54
MOTOROLA
Interrupt acknowledge bus cycles are CPU32 space cycles that are generated during
exception processing. For further information about the types of interrupt acknowledge
bus cycles determined by AVEC or DSACK, refer to APPENDIX A ELECTRICAL
CHARACTERISTICS and the SIM Reference Manual (SIMRM/AD).
Typical microcontrollers require additional hardware to provide external chip-select
and address decode signals. The MCU includes 12 programmable chip-select circuits
that can provide 2 to 16 clock-cycle access to external memory and peripherals.
Address block sizes of two Kbytes to one Mbyte can be selected. Figure 5-19 is a
diagram of a basic system that uses chip-selects.
E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC and the processor
lowing ways:
1. When there is no contention (IARB = %0000), the spurious interrupt monitor
2. The dominant interrupt source (external or internal) supplies a vector num-
3. The AVEC signal is asserted (the signal can be asserted by the dominant
4. The bus monitor asserts BERR and the CPU32 generates the spurious in-
transfers control to the exception handler routine.
asserts BERR, and the CPU32 generates the spurious interrupt vector num-
ber.
ber and DSACK signals appropriate to the access. The CPU32 acquires the
vector number.
external interrupt source or the pin can be tied low), and the CPU32 gener-
ates an autovector number corresponding to interrupt priority.
terrupt vector number.
SYSTEM INTEGRATION MODULE
USER’S MANUAL
MC68336/376