MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 123

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

5.7.3.3 Breakpoint Mode Selection
5.7.4 MCU Module Pin Function During Reset
MC68336/376
USER’S MANUAL
Background debug mode (BDM) is enabled when the breakpoint (BKPT) pin is sam-
pled at a logic level zero at the release of RESET. Subsequent assertion of the BKPT
pin or the internal breakpoint signal (for instance, the execution of the CPU32 BKPT
instruction) will place the CPU32 in BDM.
If BKPT is sampled at a logic level one at the rising edge of RESET, BDM is disabled.
Assertion of the BKPT pin or execution of the execution of the BKPT instruction will
result in normal breakpoint exception processing.
BDM remains enabled until the next system reset. BKPT is relatched on each rising
transition of RESET. BKPT is internally synchronized and must be held low for at least
two clock cycles prior to RESET negation for BDM to be enabled. BKPT assertion logic
must be designed with special care. If BKPT assertion extends into the first bus cycle
following the release of RESET, the bus cycle could inadvertently be tagged with a
breakpoint.
Refer to 4.10.2 Background Debug Mode and the CPU32 Reference Manual
(CPU32RM/AD) for more information on background debug mode. Refer to the SIM
Reference Manual (SIMRM/AD) and APPENDIX A ELECTRICAL CHARACTERIS-
TICS for more information concerning BKPT signal timing.
Usually, module pins default to port functions and input/output ports are set to the input
state. This is accomplished by disabling pin functions in the appropriate control regis-
ters, and by clearing the appropriate port data direction registers. Refer to individual
module sections in this manual for more information. Table 5-16 is a summary of mod-
ule pin function out of reset.
The MODCLK pin can also be used as parallel I/O pin PF0. To pre-
vent inadvertent clock mode selection by logic connected to port F,
use an active device to drive MODCLK during reset.
SYSTEM INTEGRATION MODULE
NOTE
MOTOROLA
5-45