MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet
MC68376BAMFT20
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MC68376BAMFT20 Summary of contents
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TouCAN is a trademark of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ...
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Paragraph 2.1 Symbols and Operators ............................................................................. 2-1 2.2 CPU32 Registers ....................................................................................... 2-2 2.3 Pin and Signal Mnemonics ........................................................................ 2-2 2.4 Register Mnemonics .................................................................................. 2-4 2.5 Conventions .............................................................................................. 2-8 3.1 MCU Features ........................................................................................... 3-1 3.1.1 Central Processing Unit (CPU32) ...................................................... 3-1 ...
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Paragraph 4.4 Virtual Memory .......................................................................................... 4-9 4.5 Addressing Modes ..................................................................................... 4-9 4.6 Processing States ..................................................................................... 4-9 4.7 Privilege Levels ....................................................................................... 4-10 4.8 Instructions .............................................................................................. 4-10 4.8.1 M68000 Family Compatibility .......................................................... 4-14 4.8.2 Special Control Instructions ............................................................. 4-14 4.8.2.1 Low-Power Stop ...
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Paragraph 5.2.4 Register Access ................................................................................ 5-3 5.2.5 Freeze Operation .............................................................................. 5-3 5.3 System Clock ............................................................................................ 5-4 5.3.1 Clock Sources ................................................................................... 5-4 5.3.2 Clock Synthesizer Operation ............................................................. 5-5 5.3.3 External Bus Clock .......................................................................... 5-12 5.3.4 Low-Power Operation ...................................................................... 5-12 5.4 System ...
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Paragraph 5.6.4.2 LPSTOP Broadcast Cycle ....................................................... 5-34 5.6.5 Bus Exception Control Cycles ......................................................... 5-34 5.6.5.1 Bus Errors ............................................................................... 5-36 5.6.5.2 Double Bus Faults ................................................................... 5-36 5.6.5.3 Retry Operation ....................................................................... 5-37 5.6.5.4 Halt Operation ......................................................................... 5-37 5.6.6 External Bus Arbitration ................................................................... ...
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Paragraph 5.10.2 Data Direction Registers ................................................................. 5-64 5.10.3 Data Registers ................................................................................. 5-64 5.11 Factory Test ............................................................................................ 5-64 SECTION 6 STANDBY RAM MODULE 6.1 SRAM Register Block ................................................................................ 6-1 6.2 SRAM Array Address Mapping ................................................................. 6-1 6.3 SRAM Array Address Space ...
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Paragraph 8.5 QADC Bus Interface .................................................................................. 8-6 8.6 Module Configuration ................................................................................ 8-6 8.6.1 Low-Power Stop Mode ...................................................................... 8-6 8.6.2 Freeze Mode ..................................................................................... 8-7 8.6.3 Supervisor/Unrestricted Address Space ........................................... 8-7 8.6.4 Interrupt Arbitration Priority ............................................................... 8-8 8.7 Test Register ............................................................................................. 8-8 ...
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Paragraph 9.1 General ...................................................................................................... 9-1 9.2 QSM Registers and Address Map ............................................................. 9-2 9.2.1 QSM Global Registers ....................................................................... 9-2 9.2.1.1 Low-Power Stop Operation ....................................................... 9-2 9.2.1.2 Freeze Operation ...................................................................... 9-3 9.2.1.3 QSM Interrupts .......................................................................... 9-3 9.2.2 QSM Pin Control Registers ...
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Paragraph 10.1 General .................................................................................................... 10-1 10.2 Address Map ........................................................................................... 10-2 10.3 Time Base Bus System ........................................................................... 10-2 10.4 Bus Interface Unit Submodule (BIUSM) .................................................. 10-3 10.4.1 STOP Effect On the BIUSM ............................................................ 10-3 10.4.2 Freeze Effect On the BIUSM ........................................................... ...
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Paragraph 10.9.10.1 PWM Duty Cycle Boundary Cases ....................................... 10-17 10.9.11 PWMSM Registers ........................................................................ 10-17 10.10 CTM4 Interrupts .................................................................................... 10-18 SECTION 11 TIME PROCESSOR UNIT 11.1 General .................................................................................................... 11-1 11.2 TPU Components .................................................................................... 11-2 11.2.1 Time Bases ..................................................................................... 11-2 11.2.2 Timer ...
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Paragraph 11.5.8 Brushless Motor Commutation (COMM) ....................................... 11-12 11.5.9 Frequency Measurement (FQM) ................................................... 11-13 11.5.10 Hall Effect Decode (HALLD) .......................................................... 11-13 11.6 Host Interface Registers ........................................................................ 11-13 11.6.1 System Configuration Registers .................................................... 11-13 11.6.1.1 Prescaler Control for TCR1 ................................................... 11-13 ...
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Paragraph 13.4.2 Receive Mask Registers .................................................................. 13-7 13.4.3 Bit Timing ........................................................................................ 13-8 13.4.3.1 Configuring the TouCAN Bit Timing ........................................ 13-9 13.4.4 Error Counters ................................................................................. 13-9 13.4.5 Time Stamp ................................................................................... 13-10 13.5 TouCAN Operation ................................................................................ 13-11 13.5.1 TouCAN Reset .............................................................................. 13-11 ...
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Paragraph D.2.3 Clock Synthesizer Control Register .................................................. D-8 D.2.4 Reset Status Register ...................................................................... D-9 D.2.5 System Integration Test Register (ECLK) ........................................ D-9 D.2.6 Port E Data Register ...................................................................... D-10 D.2.7 Port E Data Direction Register ....................................................... D-10 D.2.8 Port E ...
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Paragraph D.5.5 Port Data Direction Register ........................................................... D-30 D.5.6 QADC Control Registers ................................................................ D-31 D.5.7 QADC Status Register ................................................................... D-35 D.5.8 Conversion Command Word Table ................................................ D-37 D.5.9 Result Word Table .......................................................................... D-39 D.6 Queued Serial Module ............................................................................ D-40 D.6.1 ...
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Paragraph D.8 Time Processor Unit (TPU) .................................................................... D-73 D.8.1 TPU Module Configuration Register ............................................... D-73 D.8.2 Test Configuration Register ............................................................ D-75 D.8.3 Development Support Control Register .......................................... D-75 D.8.4 Development Support Status Register ........................................... D-76 D.8.5 TPU Interrupt Configuration Register ...
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Figure 3-1 MC68336/376 Block Diagram ........................................................................ 3-4 3-2 MC68336 Pin Assignments for 160-Pin Package .......................................... 3-5 3-3 MC68376 Pin Assignments for 160-Pin Package .......................................... 3-6 3-4 MC68336/376 Address Map ......................................................................... 3-13 3-5 Overall Memory Map .................................................................................... 3-15 3-6 Separate Supervisor ...
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Figure 8-1 QADC Block Diagram ..................................................................................... 8-1 8-2 QADC Input and Output Signals .................................................................... 8-3 8-3 Example of External Multiplexing ................................................................. 8-11 8-4 QADC Module Block Diagram ...................................................................... 8-13 8-5 Conversion Timing ....................................................................................... 8-14 8-6 Bypass Mode Conversion Timing ................................................................. ...
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Figure A-6 Fast Termination Read Cycle Timing Diagram ............................................ A-13 A-7 Fast Termination Write Cycle Timing Diagram ............................................. A-14 A-8 Bus Arbitration Timing Diagram — Active Bus Case ................................... A-15 A-9 Bus Arbitration Timing Diagram — Idle Bus Case ....................................... ...
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Figure MOTOROLA xx LIST OF ILLUSTRATIONS (Continued) Title Page MC68336/376 USER’S MANUAL ...
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Table 3-1 MC68336/376 Pin Characteristics................................................................... 3-7 3-2 MC68336/376 Output Driver Types................................................................. 3-8 3-3 MC68336/376 Power Connections.................................................................. 3-8 3-4 MC68336/376 Signal Characteristics .............................................................. 3-9 3-5 MC68336/376 Signal Functions .................................................................... 3-11 4-1 Unimplemented MC68020 Instructions ......................................................... 4-10 4-2 Instruction Set Summary ............................................................................... ...
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Table 8-5 QADC Status Flags and Interrupt Sources ................................................... 8-32 9-1 Effect of DDRQS on QSM Pin Function .......................................................... 9-4 9-2 QSPI Pins........................................................................................................ 9-8 9-3 Bits Per Transfer ........................................................................................... 9-17 9-4 SCI Pins ........................................................................................................ 9-24 9-5 Serial Frame Formats.................................................................................... 9-25 ...
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Table A-15 FCSM Timing Characteristics....................................................................... A-31 A-16 MCSM Timing Characteristics...................................................................... A-31 A-17 SASM Timing Characteristics....................................................................... A-32 A-18 DASM Timing Characteristics ...................................................................... A-33 A-19 PWMSM Timing Characteristics................................................................... A-34 B-1 MC68336 Ordering Information...................................................................... B-4 B-2 MC68376 Ordering Information...................................................................... B-5 D-1 Module Address ...
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Table D-35 CTM4 Address Map .....................................................................................D-56 D-36 Interrupt Vector Base Number Bit Field........................................................D-57 D-37 Time Base Register Bus Select Bits.............................................................D-58 D-38 Prescaler Division Ratio Select Field ...........................................................D-59 D-39 Drive Time Base Bus Field...........................................................................D-60 D-40 Counter Clock Select Field...........................................................................D-60 D-41 Drive ...
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SECTION 1 INTRODUCTION The MC68336 and the MC68376 are highly-integrated 32-bit microcontrollers, com- bining high-performance data manipulation capabilities with powerful peripheral subsystems. MC68300 microcontrollers are built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates ...
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MOTOROLA 1-2 INTRODUCTION MC68336/376 USER’S MANUAL ...
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SECTION 2 NOMENCLATURE The following nomenclature is used throughout the manual. Nomenclature used only in certain sections, such as register bit mnemonics, is defined in those sections. 2.1 Symbols and Operators — Addition — Subtraction or negation (two's complement) — ...
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CPU32 Registers A6–A0 — Address registers (index registers) A7 (SSP) — Supervisor stack pointer A7 (USP) — User stack pointer CCR — Condition code register (user portion of SR) D7–D0 — Data registers (index registers) DFC — Alternate function ...
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DSACK[1:0] — Data and Size Acknowledge DSCLK — Development Serial Clock DSI — Development Serial Input DSO — Development Serial Output ECLK — MC6800 Devices and Peripherals Bus Clock ETRIG[2:1] — QADC External Trigger EXTAL — Crystal Oscillator Input FC[2:0] ...
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Register Mnemonics BIUMCR — CTM4 BIUSM Module Configuration BIUTEST — CTM4 BIUSM Test Register BIUTBR — CTM4 BIUSM Time Base Register CANCTRL[0:2] CANICR — TouCAN Interrupt Configuration Register IFLAG — TouCAN Interrupt Flags Register IMASK — TouCAN Interrupt Masks ...
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FCSM12CNT — CTM4 FCSM12 Counter Register FCSM12SIC — CTM4 FCSM12 Status/Interrupt/Control Register HSQR[0:1] — TPU Host Sequence Registers [0:1] HSRR[0:1] — TPU Host Service Request Registers [0:1] LJSRR[0:27] — QADC Left-Justified Signed Result Registers [0:27] LJURR[0:27] — QADC Left-Justified Unsigned ...
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RAMBAL — RAM Base Address Low Register RAMMCR — RAM Module Configuration Register RAMTST — RAM Test Register ROMBAH — ROM Base Address High Register ROMBAL — ROM Base Address Low Register RR[0:F] — QSM Receive RAM RSIGHI — ROM ...
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TSTRC — SIM Test Module Repetition Counter Register TSTSC — SIM Test Module Shift Count Register TTR — TouCAN Test Register TXECTR — TouCAN Transmit Error Counter Register MC68336/376 USER’S MANUAL NOMENCLATURE MOTOROLA 2-7 ...
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Conventions Logic level one is the voltage that corresponds to a Boolean true (1) state. Logic level zero is the voltage that corresponds to a Boolean false (0) state. Set refers specifically to establishing logic level one on a ...
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This section contains information about the entire MC68336/376 modular microcon- troller. It lists the features of each module, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing ...
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Queued Analog-to-Digital Converter (QADC) • 16 channels internally directly accessible channels with external multi- plexing • Six automatic channel selection and conversion modes • Two channel scan queues of variable length, each with a variable ...
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CAN 2.0B Controller Module (TouCAN) • Full implementation of CAN protocol specification, version 2.0 A and B • 16 receive/transmit message buffers bytes data length • Global mask register for message buffers ...
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VSTBY CTM2C CTD[10:9]/CTD[4:3] CPWM[8:5] CANTX0 CANRX0 TouCAN MC68376 ONLY QSM RXD TXD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 1. PORT A PINS INCORPORATE OPEN DRAIN PULL DOWN DRIVERS Figure 3-1 MC68336/376 Block Diagram MOTOROLA 3-4 8K CTM4 3.5 TPU ...
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RXD 3 TXD/PQS7 4 PCS3/PQS6 5 PCS2/PQS5 6 PCS1/PQS4 7 PCS0/SS/PQS3 8 SCK/PQS2 9 MOSI/PQS1 10 MISO/PQS0 11 ADDR1 12 VDD 13 ADDR2 14 ADDR3 15 VSS 16 ADDR4 17 ADDR5 18 ADDR6 19 ADDR7 20 VSS ...
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CANTX0 1 2 RXD 3 TXD/PQS7 4 PCS3/PQS6 5 PCS2/PQS5 6 PCS1/PQS4 7 PCS0/SS/PQS3 8 SCK/PQS2 9 MOSI/PQS1 10 MISO/PQS0 11 ADDR1 12 VDD 13 ADDR2 14 ADDR3 15 VSS 16 ADDR4 17 ADDR5 18 ADDR6 19 ADDR7 20 VSS ...
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Table 3-1 MC68336/376 Pin Characteristics Output Pin Mnemonic Driver ADDR23/CS10/ECLK A ADDR[22:19]/CS[9:6] A ADDR[18:0] A AN[51:48] — AN[3:0]/AN[ — AN[59:57] Ba AN[56:55]/ETRIG[2:1] Ba AN[54:52]/MA[2: AVEC B BERR B BG/CS1 B BGACK/CS2 B BKPT/DSCLK — ...
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Table 3-1 MC68336/376 Pin Characteristics (Continued) Output Pin Mnemonic Driver SIZ[1:0] B T2CLK — TPUCH[15:0] A TSTME/TSC — TXD Bo 2 — XFC 2 — XTAL NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK, and the QSM and QADC ...
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Signal Descriptions The following tables define the MC68336/376 signals. Table 3-4 shows signal origin, type, and active state. Table 3-5 describes signal functions. Both tables are sorted al- phabetically by mnemonic. MCU pins often have multiple functions. More than ...
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Table 3-4 MC68336/376 Signal Characteristics (Continued) Signal Name PQA[7:0] PQB[7:0] PQS[7:0] QUOT R/W RESET RMC RXD SCK SIZ[1:0] SS T2CLK TPUCH[15:0] TSTME/TSC TXD XFC XTAL MOTOROLA 3-10 MCU Module Signal Type QADC Input/Output QADC Input QSM Input/Output SIM Output SIM ...
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Table 3-5 MC68336/376 Signal Functions Mnemonic Signal Name ADDR[23:0] Address Bus AN[59:48]/[3:0] QADC Analog Input AN[ QADC Analog Input AS Address Strobe AVEC Autovector BERR Bus Error BG Bus Grant BGACK Bus Grant Acknowledge BKPT Breakpoint BR ...
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Table 3-5 MC68336/376 Signal Functions (Continued) Mnemonic Signal Name PQA[7:0] QADC Port A PQB[7:0] QADC Port B PQS[7:0] Port QS QUOT Quotient Out R/W Read/Write RESET Reset RMC Read-Modify-Write Cycle RXD SCI Receive Data SCK QSPI Serial Clock SIZ[1:0] Size ...
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Internal Register Map In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represent determines the base address of MCU module control registers. In the MC68336/376 equal to M111, where M ...
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Address Space Maps Figure 3-5 shows a single memory space. Function codes FC[2:0] are not decoded externally so that separate user/supervisor or program/data spaces are not provided. In Figure 3-6, FC2 is decoded, resulting in separate supervisor and user ...
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COMBINED SUPERVISOR AND USER SPACE $7FF000 INTERNAL REGISTERS ( $FFF000 INTERNAL REGISTERS ( $FFFFFF NOTES: 1. LOCATION OF THE EXCEPTION VECTOR TABLE IS DETERMINED BY THE VECTOR BASE REGISTER. THE VECTOR ADDRESS IS THE CONCATENATION ...
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VECTOR OFFSET 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 SUPERVISOR 002C SPACE 0030 0034 0038 003C 0040–005C 006C 0064 0068 006C 0070 0074 0078 007C 0080–00BC 00C0–00EB 00EC–00FC 0100–03FC $7FF000 INTERNAL REGISTERS $FFF000 INTERNAL REGISTERS ...
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VECTOR OFFSET 0000 0004 VECTOR OFFSET 0008 000C 0010 0014 0018 001C 0020 0024 SUPERVISOR 0028 DATA 002C SPACE 0030 0034 0038 003C 0040–005C 006C 0064 0068 006C 0070 0074 0078 007C 0080–00BC 00C0–00EB 00EC–00FC 0100–03FC $7FF000 INTERNAL REGISTERS ...
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USER PROGRAM SPACE $FFFFFF NOTES: 1. LOCATION OF THE MODULE CONTROL REGISTERS IS DETERMINED BY THE STATE OF THE MODULE MAPPING (MM) BIT IN THE SIM CONFIGURATION REGISTER M111, WHERE M IS THE STATE OF THE MM ...
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SECTION 4 CENTRAL PROCESSOR UNIT The CPU32, the instruction processing module of the M68300 family, is based on the industry-standard MC68000 processor. It has many features of the MC68010 and MC68020, as well as unique features suited for high-performance controller ...
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CONTROL STORE CONTROL LOGIC MICROSEQUENCER AND CONTROL Figure 4-1 CPU32 Block Diagram 4.2 CPU32 Registers The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. User programs can use only the ...
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Figure 4-2 User Programming Model MC68336/376 USER’S MANUAL CENTRAL PROCESSOR UNIT DATA REGISTERS ...
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Figure 4-3 Supervisor Programming Model Supplement 4.2.1 Data Registers The eight data registers can store data operands 16, 32, and 64 bits and ad- dresses bits. The following data types are ...
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MSB HIGH-ORDER BYTE MIDDLE HIGH BYTE 31 HIGH-ORDER WORD MSB 31 Figure 4-4 Data Organization in Data Registers 4.2.2 Address Registers Each address register and stack pointer is 32 bits wide and ...
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SIGN EXTENDED 31 Figure 4-5 Address Organization in Address Registers 4.2.3 Program Counter The PC contains the address of the next instruction to be executed by the CPU32. During instruction execution and exception processing, the processor automatically increments the ...
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Alternate Function Code Registers Alternate function code registers (SFC and DFC) contain 3-bit function codes. Func- tion codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-Mbyte address spaces. The processor ...
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MSB BYTE 0 BYTE 2 15 MSB 15 MSB LONG WORD 0 LONG WORD 1 LONG WORD 2 15 MSB ADDRESS 0 ADDRESS 1 ADDRESS 2 MSB = Most Significant Bit LSB = Least Significant Bit 15 12 ...
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Virtual Memory The full addressing range of the CPU32 on the MC68336/376 is 16 Mbytes in each of eight address spaces. Even though most systems implement a smaller physical mem- ory, the system can be made to appear to ...
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The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally generated explicitly by an instruction unusual condition arising during the execution of an instruc- tion. Exception processing ...
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Table 4-2 Instruction Set Summary Dn, Dn ABCD (An), (An) Dn, <ea> ADD <ea>, Dn ADDA <ea>, An ADDI #<data>, <ea> ADDQ # <data>, <ea> Dn, Dn ADDX (An), (An) <ea>, Dn AND Dn, <ea> ANDI # <data>, <ea> ANDI ...
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Table 4-2 Instruction Set Summary (Continued) <ea> DIVSL/DIVUL <ea>, Dq <ea> EOR Dn, <ea> EORI # <data>, <ea> EORI to CCR # <data>, CCR 1 # <data>, SR EORI to SR EXG Rn, Rn ...
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Table 4-2 Instruction Set Summary (Continued) NEG <ea> NEGX <ea> NOP none NOT <ea> <ea> Dn, <ea> ORI #<data>, <ea> ORI to CCR #<data>, CCR 1 #<data>, SR ORI to SR PEA <ea> 1 none RESET Dn, Dn ...
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Table 4-2 Instruction Set Summary (Continued) <ea>, Dn TBLSN/TBLUN Dym : Dyn, Dn TRAP #<data> none TRAPcc #<data> TRAPV none TST <ea> UNLK An NOTES: 1. Privileged instruction. 4.8.1 M68000 Family Compatibility It is the philosophy of the M68000 family ...
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Loop Mode Instruction Execution The CPU32 has several features that provide efficient execution of program loops. One of these features is the DBcc looping primitive instruction. To increase the perfor- mance of the CPU32, a loop mode has been ...
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All exception vectors, except the reset vector and stack pointer, are located in super- visor data space. The reset vector and stack pointer are located in supervisor program space. Only the initial reset vector and stack pointer are fixed in ...
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Types of Exceptions An exception can be caused by internal or external events. An internal exception can be generated by an instruction error. The TRAP, TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause ...
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M68000 Family Development Support All M68000 Family members include features to facilitate applications development. These features include the following: Trace on Instruction Execution — M68000 Family processors include an instruction- by-instruction tracing facility as an aid to program development. ...
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TARGET SYSTEM Figure 4-8 Common In-Circuit Emulator Diagram TARGET SYSTEM TARGET MCU Figure 4-9 Bus State Analyzer Configuration 4.10.3 Enabling BDM Accidentally entering BDM in a non-development environment can lock up the CPU32 when the serial command interface is not ...
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Table 4-4 summarizes the processing of each source for both enabled and disabled cases. As shown in Table 4-4, the BKPT instruction never causes a transition into BDM. Source BKPT Double Bus Fault BGND Instruction BKPT Instruction 4.10.4.1 External BKPT ...
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RSREG command be the first command issued after tran- sition into BDM. Table 4-5 Polling the BDM Entry Source Source Double Bus Fault BGND Instruction Hardware Breakpoint NOTES: 1. Special status word (SSW) is ...
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Table 4-6 Background Mode Command Summary Command Read D/A Register RDREG/RAREG Write D/A Register WDREG/WAREG Read System Register Write System Register Read Memory Location Write Memory Location Dump Memory Block Fill Memory Block Resume Execution Patch User Code Reset Peripherals ...
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Current Instruction Program Counter (PCC) The PCC holds a pointer to the first word of the last instruction executed prior to tran- sition into background mode. Due to instruction pipelining, the instruction pointed to may not be the instruction ...
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CPU STATUS EXECUTION UNIT SYNCHRONIZE MICROSEQUENCER Figure 4-10 Debug Serial I/O Block Diagram The serial interface uses a full-duplex synchronous protocol similar to the serial pe- ripheral interface (SPI) protocol. The development system serves as the master of the serial ...
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S/C STATUS CONTROL BIT Figure 4-11 BDM Serial Data Word Table 4-7 CPU Generated Message Encoding Bit Command and data transfers initiated by the development system should clear bit 16. The current ...
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Deterministic Opcode Tracking CPU32 function code outputs are augmented by two supplementary signals to monitor the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each new instruction and each mid-instruction pipeline advance. The instruction fetch (IFETCH) ...
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SECTION 5 SYSTEM INTEGRATION MODULE This section is an overview of the system integration module (SIM) function. Refer to the SIM Reference Manual (SIMRM/AD) for a comprehensive discussion of SIM ca- pabilities. Refer to D.2 System Integration Module for information ...
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Figure 5-1 System Integration Module Block Diagram 5.2 System Configuration The SIM configuration register (SIMCR) governs several aspects of system operation. The following paragraphs describe those configuration options controlled by SIMCR. 5.2.1 Module Mapping Control registers for all the modules ...
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Because the SIM routes external interrupt requests to the CPU32, the SIM IARB field value is used for arbitration between internal and external interrupts of the same pri- ority. The reset value of IARB for the SIM is %1111, and ...
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System Clock The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral bus. Because the MCU is a fully static design, register and memory contents are not affected when the clock ...
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To generate a reference frequency using the crystal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. Typically, a 4.194 MHz crystal is used, but the frequency may vary between 1 and 6 MHz. Figure 5-3 ...
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A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To maintain a 50% clock duty cycle, the VCO frequency (f the system clock frequency, depending on the state of the X bit in SYNCR. The clock ...
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When the clock synthesizer is used, SYNCR determines the system clock frequency and certain operating parameters. The W and Y[5:0] bits are located in the PLL feed- back path, enabling frequency multiplication by a factor 256. When ...
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Table 5-2 Clock Control Multipliers Modulus Y [W: 000000 .03125 000001 .0625 000010 .09375 000011 000100 .15625 000101 .1875 000110 .21875 000111 001000 .21825 001001 .3125 001010 .34375 001011 001100 .40625 001101 .4375 001110 .46875 001111 010000 .53125 ...
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Table 5-2 Clock Control Multipliers (Continued) Modulus Y [W: 100000 1.03125 100001 1.0625 100010 1.09375 100011 1.125 100100 1.15625 100101 1.1875 100110 1.21875 100111 101000 1.28125 101001 1.3125 101010 1.34375 101011 1.375 101100 1.40625 101101 1.4375 101110 1.46875 ...
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Table 5-3 System Frequencies from 4.194 MHz Reference Modulus Y [W: 000000 131 kHz 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 ...
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Table 5-3 System Frequencies from 4.194 MHz Reference (Continued) Modulus Y [W: 100000 4325 kHz 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 ...
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External Bus Clock The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the E- clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for M6800 devices and peripherals. ECLK frequency can ...
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SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP NO USING EXTERNAL CLOCK? YES USE SYSTEM CLOCK AS SIMCLK IN LPSTOP? YES SET STSIM = WANT CLKOUT ON IN LPSTOP? YES SET STEXT = 1 SET STEXT ...
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System Protection The system protection block preserves reset status, monitors internal activity, and pro- vides periodic interrupt generation. Figure 5 block diagram of the submodule. 9 CLOCK 2 PRESCALER Figure 5-6 System Protection Block 5.4.1 Reset Status ...
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BMT[1:0] The monitor does not check DSACK response on the external bus unless the CPU32 initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter- nal to external bus cycles system contains ...
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Both writes must occur before time-out in the order listed. Any number of instructions can be executed between the two writes. Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the software watchdog timing (SWT[1:0]) field ...
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Figure 5 block diagram of the watchdog timer and the clock control for the pe- riodic interrupt timer. EXTAL XTAL FREEZE CRYSTAL 128 OSCILLATOR CLOCK SELECT AND DISABLE SOFTWARE WATCHDOG RESET LPSTOP SWE SWT1 SWT0 Figure 5-7 Periodic ...
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Either clock signal selected by the PTP is divided by four before driving the modulus counter. The modulus counter is initialized by writing a value to the periodic interrupt timer modulus (PITM[7:0]) field in PITR. A zero value turns off ...
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Low-Power STOP Mode Operation When the CPU32 executes the LPSTOP instruction, the current interrupt priority mask is stored in the clock control logic, internal clocks are disabled according to the state of the STSIM bit in the SYNCR, and ...
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DSACK1 DSACK0 R/W CS3 CS4 IRQ7 ADDR[17:0] DATA[15: CSBOOT CS0 CS1 CS2 MOTOROLA 5- ...
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The external bus has 24 address lines and 16 data lines. The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word transfers. Port width is the maximum number of bits accepted or provided ...
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Data Strobe Data strobe (DS timing signal. For a read cycle, the MCU asserts DS to signal an external device to place data on the bus asserted at the same time as AS during a ...
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Table 5-10 Address Space Encoding FC2 The supervisor bit in the status register determines whether the CPU is operating in supervisor or user mode. Addressing mode and the instruction being executed deter- ...
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When the MCU completes a bus cycle with the HALT signal asserted, DATA[15:0] is placed in a high-impedance state and bus control signals are driven inactive; the ad- dress, function code, size, and read/write signals remain in the same state. ...
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The MCU always attempts to transfer the maximum amount of data on all bus cycles. For any bus access assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are designated as shown ...
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Operand Transfer Cases Table 5- summary of how operands are aligned for various types of transfers. OPn entries are portions of a requested operand that are read or written during a bus cycle and are defined by ...
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Bus cycles terminated by DSACK assertion normally require a minimum of three CLK- OUT cycles. To support systems that use CLKOUT to generate DSACK and other in- puts, asynchronous input setup time and asynchronous input hold times are specified. When ...
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If bus termination signals remain unasserted, the MCU will continue to insert wait states, and the bus cycle will never end peripheral responds to an access access is invalid, external logic should assert the BERR ...
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Write Cycle During a write cycle, the MCU transfers data to an external memory or peripheral de- vice. If the instruction specifies a long-word or word operation, the MCU attempts to write two bytes at once. For a byte ...
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Fast Termination Cycles When an external device has a fast access time, the chip-select circuit fast termination option can provide a two-cycle external bus transfer. Because the chip-select circuits are driven from the system clock, the bus cycle termination ...
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FUNCTION CODE 2 BREAKPOINT ACKNOWLEDGE 2 LOW POWER STOP BROADCAST 2 0 INTERRUPT ACKNOWLEDGE Figure 5-12 CPU Space Address Encoding 5.6.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined ...
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External breakpoint circuitry decodes the function code and address lines, places an instruction word on the data bus, and asserts BERR. The CPU32 then performs hard- ware breakpoint exception processing: it acquires the number of the hardware break- point exception ...
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BREAKPOINT OPERATION FLOW CPU32 ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED: 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE BREAKPOINT NUMBER ON ADDR[4:2] 5) CLEAR T-BIT (ADDR1) ...
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LPSTOP Broadcast Cycle Low-power stop mode is initiated by the CPU32. Individual modules can be stopped by setting the STOP bits in each module configuration register, or the SIM can turn off system clocks after execution of the LPSTOP ...
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Bus Error Termination — BERR is asserted in lieu of, at the same time as, or before DSACK (case 3), or after DSACK (case 4), and HALT remains negated; BERR is negated at the same time or after DSACK. ...
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If DSACK or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. 5.6.5.1 Bus Errors The CPU32 treats bus errors as a type of exception. Bus error exception processing begins when the CPU32 ...
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Multiple bus errors within a single instruction that can generate multiple bus cycles cause a single bus error exception after the instruction has been executed. Immediately after assertion of a second BERR, the MCU halts and drives the HALT line ...
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When the MCU completes a bus cycle while the HALT signal is asserted, the data bus goes into a high-impedance state and the AS and DS signals are driven to their inac- tive states. Address, function code, size, and read/write ...
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This additional BG assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus. Refer to Figure 5-15, which shows bus arbitration for a single device. The flowchart shows BR negated at ...
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SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion of the data bus is valid during the cycle. During a byte write to an internal address, the portion of the bus that represents the byte that is ...
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XTRST (external reset) drives the external reset pin. 2. CLKRST (clock reset) resets the clock module. 3. MSTRST (master reset) goes to all other internal circuits. 4. SYSRST (system reset) indicates to internal circuits that the CPU32 has executed ...
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Mode Select Pin DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA11 MODCLK BKPT NOTES: 1. The DATA11 bus must remain high during reset to ensure normal operation. 5.7.3.1 Data Bus Mode Selection All data lines have weak ...
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DATA15 DATA8 DATA7 DATA0 820 RESET DS R/W Figure 5-16 Preferred Circuit for Data Bus Mode Select Conditioning Alternate methods can be used for driving data bus pins low during reset. Figure ...
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DATA PIN 1 kW 1N4148 RESET Figure 5-17 Alternate Circuit for Data Bus Mode Select Conditioning Data bus mode select current is specified in Table A-5. Do not confuse pin function with pin electrical state. Refer to 5.7.5 Pin States ...
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The MODCLK pin can also be used as parallel I/O pin PF0. To pre- vent inadvertent clock mode selection by logic connected to port F, use an active device to drive MODCLK during reset. 5.7.3.3 Breakpoint Mode Selection Background debug ...
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Table 5-16 Module Pin Functions During Reset Module CPU32 CTM4 QADC QSM TouCAN (MC68376 only) TPU 5.7.5 Pin States During Reset It is important to keep the distinction between pin function and pin electrical state clear. Although control register values ...
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Table 5-17 SIM Pin Reset States Pin(s) CS10/ADDR23/ECLK CS[9:6]/ADDR[22:19]/PC[6:3] ADDR[18:0] AS/PE5 AVEC/PE2 BERR CS1/BG CS2/BGACK CS0/BR CLKOUT CSBOOT DATA[15:0] DS/PE4 DSACK0/PE0 DSACK1/PE1 CS[5:3]/FC[2:0]/PC[2:0] HALT IRQ[7:1]/PF[7:1] MODCLK/PF0 R/W RESET RMC/PE3 SIZ[1:0]/PE[7:6] TSTME/TSC 5.7.5.2 Reset States of Pins Assigned to Other MCU ...
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When an external device asserts RESET for the proper period, reset control logic clocks the signal into an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the RESET ...
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Figure 5- timing diagram for power-on reset. It shows the relationships between RESET and bus signals. DD CLKOUT VCO LOCK CLOCKS RESET BUS CYCLES ADDRESS AND BUS STATE CONTROL SIGNALS UNKNOWN THREE-STATED NOTES: ...
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Reset Processing Summary To prevent write cycles in progress from being corrupted, a reset is recognized at the end of a bus cycle instead instruction boundary. Any processing in progress at the time a reset occurs ...
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At the release of reset, the exception vector table is located beginning at address $000000. This value can be changed by programming the vector base register (VBR) with a new value. Multiple vector tables can be used. Refer to 4.9 ...
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The CPU32 does not latch the priority of a pending interrupt request interrupt source of higher priority makes a service request while a lower priority request is pend- ing, the higher priority request is serviced interrupt ...
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When arbitration is complete, the module with both the highest asserted interrupt level and the highest arbitration priority must terminate the bus cycle. Internal modules place an interrupt vector number on the data bus and generate appropriate internal cycle termination ...
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E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol- lowing ways: 1. When there is no contention (IARB = %0000), the spurious interrupt monitor asserts BERR, and the CPU32 generates the spurious interrupt vector num- ...
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DSACK1 DSACK0 R/W CS3 CS4 IRQ7 ADDR[17:0] DATA[15: CSBOOT CS0 CS1 CS2 Figure 5-19 Basic MCU System MC68336/376 USER’S MANUAL ...
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Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Chip-select logic can also generate DSACK and AVEC signals internally. A single DSACK generator is shared by all chip-selects. Each signal ...
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Chip-Select Registers Each chip-select pin can have one or more functions. Chip-select pin assignment reg- isters CSPAR[0:1] determine functions of the pins. Pin assignment registers also de- termine port size (8- or 16-bit) for dynamic bus allocation. A pin ...
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Table 5-19 Pin Assignment Field Encoding CSxPA[1:0] Port size determines the way in which bus transfers to an external address are allo- cated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as ...
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Table 5-20 Block Size Encoding BLKSZ[2:0] 000 001 010 011 100 101 110 111 The chip-select address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be ...
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The STRB bit controls the timing of a chip-select assertion in asynchronous mode. Se- lecting address strobe causes a chip-select signal to be asserted synchronized with the address strobe. Selecting data strobe causes a chip-select signal to be asserted synchronized ...
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When a match occurs, the chip-select signal is asserted. Assertion occurs at the same time assertion in asynchronous mode. Assertion is synchronized with ECLK in synchronous mode. In asynchronous mode, the value of the DSACK field ...
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Because address match logic functions only after the EBI transfers an interrupt ac- knowledge cycle to the external address bus following IARB contention, chip-select logic generates AVEC or DSACK signals only in response to interrupt requests from external IRQ pins. ...
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Table 5-21 Chip-Select Base and Option Register Reset Values Async/sync mode Upper/lower byte Address space Following reset, the MCU fetches the initial stack pointer and program counter values from the exception vector table, beginning at $000000 in supervisor program space. ...
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Parallel Input/Output Ports Sixteen SIM pins can be configured for general-purpose discrete input and output. Al- though these pins are organized into two ports, port E and port F, function assignment is by individual pin. Pin assignment registers, data ...
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SECTION 6 STANDBY RAM MODULE The standby RAM (SRAM) module consists of a control register block and a 4-Kbyte array of fast (two bus cycle) static RAM. The SRAM is especially useful for system stacks and variable storage. The SRAM ...
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Table 6-1 shows RASP[1:0] field encodings. Table 6-1 SRAM Array Address Space Type RASP[1:0] Refer to 4.5 Addressing Modes for more information on addressing modes. Refer to 5.5.1.7 Function Codes for more information concerning address space types and program/data space ...
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Reset Reset places the SRAM in low-power stop mode, enables program space access, and clears the base address registers and the register lock bit. These actions make it pos- sible to write a new base address into the registers. ...
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MOTOROLA 6-4 STANDBY RAM MODULE MC68336/376 USER’S MANUAL ...
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SECTION 7 MASKED ROM MODULE The masked ROM module (MRM) consists of a fixed-location control register block and an 8-Kbyte mask-programmed read-only memory array that can be mapped to any 8-Kbyte boundary in the system memory map. The MRM can ...
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MRM Array Address Space Type ASPC[1:0] in MRMCR determines ROM array address space type. The module can respond to both program and data space accesses or to program space accesses only. This allows code to be executed from ROM, ...
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Low-Power Stop Mode Operation Low-power stop mode minimizes MCU power consumption. Setting the STOP bit in MRMCR places the MRM in low-power stop mode. In low-power stop mode, the array cannot be accessed. The reset state of STOP is ...
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MOTOROLA 7-4 MASKED ROM MODULE MC68336/376 USER’S MANUAL ...
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SECTION 9 QUEUED SERIAL MODULE This section is an overview of the queued serial module (QSM). Refer to the QSM Reference Manual (QSMRM/AD) for complete information about the QSM. 9.1 General The QSM contains two serial interfaces, the queued serial ...
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The SCI provides a standard non-return to zero (NRZ) mark/space format. It operates in either full- or half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers. A modulus-type baud rate generator provides rates from 110 ...
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Freeze Operation The FRZ[1:0] bits in QSMCR are used to determine what action is taken by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the CPU32 en- ters background debug mode. At the present ...
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QSM Pin Control Registers The QSM uses nine pins. Eight of the pins can be used for serial communication or for parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns the corresponding pin to ...
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Queued Serial Peripheral Interface The queued serial peripheral interface (QSPI) is used to communicate with external devices through a synchronous serial bus. The QSPI is fully compatible with SPI sys- tems found on other Motorola products, but has enhanced ...
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Serial transfers of eight to sixteen can be specified. Programmable transfer length sim- plifies interfacing to devices that require different data lengths. An inter-transfer delay 8192 system clocks can be specified (default is 17 sys- tem clocks). ...
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Reads of SPCR2 return the current value of the register, not of the buffer. Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect on ...
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Command RAM Command RAM is used by the QSPI in master mode. The CPU32 writes one byte of control information to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM. Command ...
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The internal pointer is initialized to the same value as NEWQP. During normal opera- tion, the command pointed to by the internal pointer is executed, the value in the inter- nal pointer is copied into CPTQP, the internal pointer is ...
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Figure 9-4 Flowchart of QSPI Initialization Operation MOTOROLA 9-10 BEGIN CPU32 INITIALIZES QSM GLOBAL REGISTERS CPU32 INITIALIZES PQSPAR, PORTQS, AND DDRQS IN THIS ORDER CPU32 INITIALIZES QSPI CONTROL REGISTERS CPU32 INITIALIZES QSPI RAM CPU32 ENABLES QSPI Y MSTR = 1 ...
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Figure 9-5 Flowchart of QSPI Master Operation (Part 1) MC68336/376 USER’S MANUAL QSPI CYCLE BEGINS (MASTER MODE QSPI DISABLED N Y HAS NEWQP BEEN WRITTEN N READ COMMAND CONTROL AND TRANSMIT DATA FROM RAM USING QUEUE POINTER ...
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Figure 9-6 Flowchart of QSPI Master Operation (Part 2) MOTOROLA 9-12 B1 WRITE QUEUE POINTER TO CPTQP STATUS BITS Y IS CONTINUE BIT ASSERTED N NEGATE PERIPHERAL CHIP-SELECT(S) IS DELAY Y AFTER TRANSFER EXECUTE PROGRAMMED DELAY ASSERTED N EXECUTE STANDARD ...
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C1 IS THIS THE Y LAST COMMAND IN THE QUEUE N INCREMENT WORKING QUEUE POINTER IS HALT Y OR FREEZE ASSERTED N A1 Figure 9-7 Flowchart of QSPI Master Operation (Part 3) MC68336/376 USER’S MANUAL ASSERT SPIF STATUS FLAG IS ...
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Figure 9-8 Flowchart of QSPI Slave Operation (Part 1) MOTOROLA 9-14 QSPI CYCLE BEGINS (SLAVE MODE QSPI Y DISABLED N Y HAS NEWQP CHANGED TO NEWQP BEEN WRITTEN N READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS ...
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C2 IS THIS THE Y LAST COMMAND IN THE QUEUE N INCREMENT WORKING QUEUE POINTER IS HALT Y OR FREEZE ASSERTED N A2 Figure 9-9 Flowchart of QSPI Slave Operation (Part 2) MC68336/376 USER’S MANUAL ASSERT SPIF STATUS FLAG IS ...
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Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus master supplies the clock signal SCK to time the transfer of data. Four possible combinations of clock phase and polarity can be specified by the ...
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Baud rate is selected by writing a value from 2 to 255 into SPBR[7:0] in SPCR0. The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock. The following expressions apply to SCK baud rate: ...
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Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to com- plete conversion. Writing a value to DTL[7:0] in SPCR1 specifies a delay ...
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Master Wrap-Around Mode Wrap-around mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address $ the address pointed to by NEWQP, depending on the state of the WRTO bit in ...
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Because the command RAM is not used in slave mode, the CONT, BITSE, DT, DSCK, and peripheral chip-select bits have no effect. The PCS0/SS pin is used only as an in- put. The SPBR, DT and DSCKL fields in SPCR0 ...
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To configure a peripheral chip-select, set the appropriate bit in PQSPAR, then config- ure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value of the bit in PORTQS that corresponds to the chip-select pin ...
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TRANSMITTER BAUD RATE CLOCK 15 SCCR1 CONTROL REGISTER 1 TDRE TC SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 9-10 SCI Transmitter Block Diagram MOTOROLA 9-22 SCDR Tx BUFFER 10 (11)-BIT Tx SHIFT REGISTER H ( ...
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RECEIVER BAUD RATE CLOCK RxD PIN BUFFER PARITY DETECT WAKE-UP LOGIC 15 SCCR1 CONTROL REGISTER 1 15 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 9-11 SCI Receiver Block Diagram MC68336/376 USER’S MANUAL 16 DATA H RECOVERY 0 SCSR STATUS REGISTER ...
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Status Register SCSR contains flags that show SCI operating conditions. These flags are cleared ei- ther by SCI hardware or by reading SCSR, then reading or writing SCDR. A long-word read can consecutively access both SCSR and SCDR. This ...
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Definition of Terms • Bit-Time — The time required to transmit or receive one bit of data, which is equal to one cycle of the baud frequency. • Start Bit — One bit-time of logic zero that indicates the ...
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SCBR[12:0] where SCBR[12: the range { ..., 8191}. The SCI receiver operates asynchronously. An internal clock is necessary to synchro- nize with an incoming data stream. The SCI baud rate generator produces a receive time sampling ...
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Data to be transmitted is written to SCDR, then transferred to the serial shifter. The transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When TDRE = 0, the TDR contains data that has not been ...
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Receiver Operation The RE bit in SCCR1 enables ( and disables ( the receiver. The receiver contains a receive serial shifter and a parallel receive data register (RDR) lo- cated in the SCI data register ...
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The SCI receiver has both short and long idle-line detection capability. Idle-line detec- tion is always enabled. The idle line type (ILT) bit in SCCR1 determines which type of detection is used. When an idle line condition is detected, the ...
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Internal Loop The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter. When LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter ...
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Set up SCCR1 a. Select serial mode (M) b. Enable use (PE) and type (PT) of parity check. c. Select use (RWU) and type (WAKE) of receiver wake-up. d. Enable idle-line detection (ILT) and interrupt (ILIE). e. Enable or ...
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MOTOROLA 9-32 QUEUED SERIAL MODULE MC68336/376 USER’S MANUAL ...
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SECTION 8 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE This section is an overview of the queued analog-to-digital converter (QADC) module. Refer to the QADC Reference Manual (QADCRM/AD) for a comprehensive discussion of QADC capabilities. 8.1 General The QADC consists of an analog ...
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QADC Address Map The QADC occupies 512 bytes of address space. Nine words are control, port, and status registers, 40 words are the CCW table, and 120 words are the result word table because 40 result registers can be ...
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The QADC allows external trigger inputs and the multiplexer outputs to be combined onto some of the channel pins. All of the channel pins are used for at least two func- tions, depending on the modes in use. The following ...
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Port A Analog Input Pins When used as analog inputs, the eight port A pins are referred to as AN[59:52]. Due to the digital output drivers associated with port A, the analog characteristics of port A are different from ...
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External Trigger Input Pins The QADC has two external trigger pins (ETRIG[2:1]). The external trigger pins share two multifunction port A pins (PQA[4:3]), which are normally used as analog channel input pins. Each of the two external trigger pins ...
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Dedicated Analog Supply Pins V and V pins supply power to the analog subsystems of the QADC module. DDA SSA Dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the ...
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In the low-power stop mode, QADCMCR, the interrupt register (QADCINT), and the test register (QADCTEST) are not reset and fully accessible. The data direction regis- ter (DDRQA) and port data registers (PORTQA and PORTQB) are not reset and are read-only ...
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The SUPV bit in QADCMCR designates the assignable space as supervisor or unrestricted. Attempts to read supervisor-only data space when the CPU32 is not in supervisor mode causes a value of $0000 to be returned. Attempts to ...
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There are two special cases to consider for digital I/O port operation. When the MUX (externally multiplexed) bit is set in QACR0, the data direction register settings are ig- nored for the bits corresponding to PQA[2:0], the three multiplexed address ...
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External Multiplexing Operation External multiplexers concentrate a number of analog signals onto a few inputs to the analog converter. This is helpful in applications that need to convert more analog sig- nals than the A/D converter can normally provide. ...
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AN0 AN2 AN4 AN6 MUX AN8 AN10 AN12 AN14 AN1 AN3 AN5 AN7 MUX AN9 AN11 AN0/ANW/PQB0 AN13 AN1/ANX/PQB1 AN15 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN16 AN49/PQB5 AN18 AN50/PQB6 AN20 AN51/PQB7 AN22 MUX AN52/MA0/PQA0 AN24 AN26 AN53/MA1/PQA1 AN28 AN54/MA2/PQA2 AN30 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 ...
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Analog Input Channels The number of available analog channels varies, depending on whether or not exter- nal multiplexing is used. A maximum of 16 analog channels are supported by the in- ternal multiplexing circuitry of the converter. Table 8-2 ...
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CHAN. MUX CHARGE PQA7 16: 2 PUMP AND BIAS SAMPLE/ HOLD SAMPLE/ PQA0 HOLD PQB7 MUX 4: 1 PQB0 10-BIT RC-DAC VRH DUMMY DAC VRL VDDA COMPAR- ATOR VSSA Figure 8-4 QADC Module Block Diagram 8.11.1 Conversion Cycle Times Total ...
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Figure 8-5 illustrates the timing for conversions. This diagram assumes a final sampling period of two QCLKs. INITIAL TRANSFER SAMPLE TIME TIME 2 CYCLES 4 CYCLES QCLK SAMPLE AND TRANSFER TIME 8.11.1.1 Amplifier Bypass Mode Conversion Timing If the amplifier ...
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SAMPLE TIME N CYCLES: ( 16) QCLK SAMPLE TIME Figure 8-6 Bypass Mode Conversion Timing 8.11.2 Front-End Analog Multiplexer The internal multiplexer selects one of the 16 analog input pins or one of three special internal reference channels ...
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Comparator The comparator is used during the approximation process to sense whether the digi- tally selected arrangement of the DAC array produces a voltage level higher or lower than the sampled input. The comparator output feeds into the SAR ...
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Table 8-3 Queue 1 Priority Assertion Queue State A trigger event for queue 1 or queue 2 causes the corresponding queue execution Inactive to begin. Queue 2 cannot begin execution until queue 1 reaches completion or the paused Queue 1 ...
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CONVERSION COMMAND WORD (CCW) TABLE BEGIN QUEUE PAUSE PAUSE END OF QUEUE 1 0 BQ2 0 BEGIN QUEUE 2 1 PAUSE 0 1 PAUSE 0 PAUSE ...