MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 275

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

13.7 Interrupts
MC68336/376
USER’S MANUAL
The TouCAN is capable of generating one interrupt level on the IMB. This level is
programmed into the priority level bits in the interrupt configuration register (CANICR).
This value determines which interrupt signal is driven onto the bus when an interrupt
is requested.
When an interrupt is requested, the CPU32 initiates an IACK cycle. The TouCAN
decodes the IACK cycle and compares the CPU32 recognized level to the level that it
is currently requesting. If a match occurs, then arbitration begins. If the TouCAN wins
arbitration, it generates a uniquely encoded interrupt vector that indicates which event
is requesting service. This encoding scheme is as follows:
Figure 13-5 shows a block diagram of the interrupt hardware.
Each one of the 16 message buffers can be an interrupt source, if its corresponding
IMASK bit is set. There is no distinction between transmit and receive interrupts for a
particular buffer. Each of the buffers is assigned a bit in the IFLAG register. An IFLAG
bit is set when the corresponding buffer completes a successful transmission/recep-
tion. An IFLAG bit is cleared when the CPU32 reads IFLAG while the associated bit is
set, and then writes it back as zero (and no new event of the same type occurs be-
tween the read and the write actions).
INTERRUPT
REQUEST
LEVEL
(ILCAN[2:0]
MASKS
BUFFER
INTERRUPTS
BUS OFF
ERROR
WAKE UP
VECTOR
BASE
ADDRESS
(IVBA[2:0])
• The higher-order bits of the interrupt vector come from the IVBA[2:0] field in
• The low-order five bits are an encoded value that indicate which of the 19
CANICR.
TouCAN interrupt sources is requesting service.
Figure 13-5 TouCAN Interrupt Vector Generation
19
16
CAN 2.0B CONTROLLER MODULE (TouCAN)
INTERRUPT
ENABLE
LOGIC
3
3
19
INTERRUPT
PRIORITY
ENCODER
INTERRUPT
LEVEL
DECODER
7
5
3
MODULE
INTERRUPT
VECTOR
IRQ[7:1]
TOUCAN INTERRUPT GEN
MOTOROLA
13-19