MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 347

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

QADCINT — QADC Interrupt Register
FRZ — FREEZE Assertion Response
SUPV — Supervisor/Unrestricted Data Space
IARB[3:0] — Interrupt Arbitration ID
D.5.2 QADC Test Register
QADCTEST — QADC Test Register
D.5.3 QADC Interrupt Register
IRLQ1[2:0] — Queue 1 Interrupt Level
IRLQ2[2:0] — Queue 2 Interrupt Level
MC68336/376
USER’S MANUAL
RESET:
NOTES:
RSVD
15
1. Bits 1 and 0 are supplied by the QADC.
The FRZ bit determines whether or not the QADC responds to assertion of the IMB
FREEZE signal.
The SUPV bit designates the assignable space as supervisor or unrestricted.
The IARB field is used to arbitrate between simultaneous interrupt requests of the
same priority. Each module that can generate interrupt requests must be assigned a
unique, non-zero IARB field value.
Used for factory test only.
When queue 1 generates an interrupt request, IRLQ1[2:0] determines which of the
interrupt request signals is asserted. When a request is acknowledged, the QADC
compares IRLQ1[2:0] to a mask value supplied by the CPU32 to determine whether
to respond. IRLQ1[2:0] must have a value in the range of $0 (interrupts disabled) to $7
(highest priority).
When queue 2 generates an interrupt request, IRLQ2[2:0] determines which of the
interrupt request signals is asserted. When a request is acknowledged, the QADC
compares IRLQ2[2:0] to a mask value supplied by the CPU32 to determine whether
to respond. IRLQ2[2:0] must have a value in the range of $0 (interrupts disabled) to $7
(highest priority).
0 = QADC ignores the IMB FREEZE signal.
1 = QADC finishes any current conversion, then freezes.
0 = Only the module configuration register, test register, and interrupt register are
1 = All QADC registers and tables are designated as supervisor-only data space.
14
0
designated as supervisor-only data space. Access to all other locations is
unrestricted.
IRLQ1[2:0]
13
0
12
0
RSVD
11
10
0
REGISTER SUMMARY
IRLQ2[2:0]
9
0
8
0
7
0
6
0
5
0
IVB[7:2]
4
0
3
1
2
1
MOTOROLA
$YFF202
$YFF204
1
1
IVB[1:0]
D-29
1
0
1