M69030 Asiliant Technologies, M69030 Datasheet - Page 95

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

IOSS
read/write at I/O address 3CDh
shared between both pipelines A and B
Note: Regardless of the setting of ANY bit in THIS register, this register is ALWAYS both readable and
writable from the I/O space.
This register controls access to all registers accessible from the I/O space, except itself. FCR, MSR, MSS,
ST00 and ST01 are all direct-access registers, and are therefore controlled differently from any of the sub-
indexed registers. Also, the AR and DAC sub-indexed register groups do not have the ability to share the
use of a single set of indices. Due to functional quirks imposed by VGA compatibility considerations, the
sets of indices for these registers in each of the pipelines can be used only with the corresponding sets of
sub-indexed registers also belonging to that pipeline. In contrast, VGA compatibility considerations forced
fewer restrictions on the CR, GR and SR registers, and the same absence of restrictions exist with the FR,
MR and XR registers which are Intel extensions.
Read and write access to the direct-access registers (FCR, MSR, MSS, ST00 and ST01) is controlled
entirely by bits 2 through 0 of this register. Bit 2 selects which pipeline’s set of these direct-access registers
will respond to read accesses. Bits 1 and 0 select which pipeline’s set of these direct-access registers will
be writable.
Read and write access to the AR and DAC sub-indexed registers, as well as their indices, is controlled by
bits 2 through 0 of this register – bits 4 and 3 in no way control access to these sub-indexed registers or
their indices. Bit 2 selects which pipeline’s set of these sub-indexed registers and corresponding indices
will respond to read accesses. Bits 1 and 0 select which pipeline’s set of these sub-indexed registers and
corresponding indices will be writable.
Read and write access to the CR, FR, GR, MR, SR and XR sub-indexed registers is controlled by bits 2
through 0 of this register. Read and write access to the indices for these sub-indexed registers is controlled
by bits 4 and 3. Bit 2 selects which pipeline’s set of these sub-indexed registers will respond to read
accesses. Bits 1 and 0 select which pipeline’s set of these sub-indexed registers will be writable. Bit 3
allows the independent selection of which pipeline’s set of indices for these sub-indexed registers will be
used in making accesses to the actual sub-indexed registers. Bit 4 allows the independent control of write
access to whichever set of indices is selected by bit 3.
7-5
`efmp
A
&
B

Reserved
69030 Databook
7
I/O Space Shadowing Register
These bits always return the value of 0 when read.
Reserved
(000)
6
General Control and Status Registers
5
Write En
Index
(0)
4
Index A/B
Select
(0)
3
Rd Select
Register
(0)
2
Sel & Read-Mode Ctrl
I/O Space Reg Write
Revision 1.3 11/24/99
1
(00)
0
8-7