M69030 Asiliant Technologies, M69030 Datasheet - Page 247

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

FR05
read/write at I/O address 3D1h with index at I/O address 3D0h set to 05h
shared by both pipelines A and B
7-5
4
3
2-0
`efmp
A
&
B

Reserved
Host Interface Disable
Screen Refresh Disable
Normal Refresh Count
69030 Databook
7
Miscellaneous Control Register
These bits always return the value of 0 when read.
0: The host interface is enabled and functions normally. All registers and memory locations
are accessible by the host CPU as usual. This is the default after reset.
1: The host interface is disabled. All registers and memory locations become inaccessible
to the host CPU, and all pins of the host interface are ignored except for the RESET# pin.
The host interface can be re-enabled (and this bit cleared to 0, as a result) only by a
hardware reset via the RESET# pin or a low-to-high transition on the STNDBY# pin.
0: Screen refresh enabled for both pipelines, i.e, normal operation. This is the default after
reset.
1: Screen refresh disabled for both pipelines. In other words, no on-screen image data is
being scanned out of the frame buffer for either pipeline. The frame buffer and all graphics
controller registers remain accessible.
These bits specify the number of memory refresh cycles per scanline. However, there is
guaranteed a minimum of 1 refresh cycle per scanline regardless of whether these bits are
set to 001 or 000.
Reserved
(000)
6
5
Flat Panel Registers
Host I/F
Disable
(0)
4
Refresh Dis
Screen
(0)
3
2
Normal Refresh Count
Revision 1.3 11/24/99
(000)
1
0
15-9