M69030 Asiliant Technologies, M69030 Datasheet - Page 342

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

B-2
PLL Parameters
Each phase-locked loop consists of the elements shown in the figure below. The reference input frequency
(14.31818MHz) is divided by N, a 8-bit programmable value. The output of the VCO is divided by 1 (or 4
via the VCO Loop Divider: VLD) and then further divided by M, another 8-bit programmable value. The
phase detector compares the N and M results and adjusts the VCO frequency as needed to achieve
frequency equality.
When the loop has stabilized, the VCO frequency (F
For VLD =1, the F
The VCO output can be further divided by 1, 2, 4, 8, 16, or 32 (which is called Post Divisor: PD) to produce
the final DCLK or MCLK used for video or memory timing.
Therefore the output frequency is:
By “fine tuning” the M/N ratio in each PLL, extremely small adjustments in the exact DCLK and MCLK
frequencies can be achieved. The VCO itself is designed to operate in the range of 100MHz to 220 MHz.
`efmp
REFCLK
14.3MHz

If VLD=1:
If VLD=4:
(DCLK only)
69030 Databook
M counter = Program value M’+2
N counter = Program value N’+2
VCO
N
÷
can be written as:
or
Detect
Phase
÷M
Figure B-1: PLL Elements
F
F
F
F
VCO
VCO
VCO
OUT
Charge Pump
Clock Generation
(DCLK only)
Divide (VLD)
VCO Loop
& Filter
(÷4, ÷1)
= (F
/M = F
/4M = F
= (F
VCO
REF
VCO
REF
REF
)/PD
) is related to the reference as follows:
*M /N)
F
/ N
F
OUT
/ N.
VCO
: Output frequency: (desired frequency)
: VCO frequency (before post divisor)
VCO
F
VCO
Post Divisor
8, 16, 32
÷1, 2, 4,
(PD)
Revision 1.3 11/24/99
F
OUT
CLK