M69030 Asiliant Technologies, M69030 Datasheet - Page 150
M69030
Manufacturer Part Number
M69030
Description
Manufacturer
Asiliant Technologies
Datasheet
1.M69030.pdf
(387 pages)
Specifications of M69030
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
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10-2
SRX
read/write at I/O address 3C4h
This register is cleared to 00h by reset.
7-3
2-0
SR00
read/write at I/O address 3C5h with index at address 3C4h set to 00h
shared by both pipelines A and B
7-2
1
0
`efmp
A
&
B
7
Reserved
Sequencer Register Index
Reserved
Synchronous Reset
Asynchronous Reset
69030 Databook
7
Sequencer Index Register
Reset Register
These three bits are used to select any one of the sequencer registers, SR00 through
SR07, to be accessed via the data port at I/O location 3C5.
Note: SR02 is referred to in the VGA standard as the Map Mask Register. However, the
word “map” is used with multiple meanings in the VGA standard and was therefore deemed
too confusing, hence the reason for calling it the Plane Mask Register.
Note: SR07 is a standard VGA register that was not documented by IBM.
It is not a Intel extension.
Setting this bit to 0 commands the sequencer to perform a synchronous clear and then halt.
The sequencer should be reset via this bit before changing the Clocking Mode Register
(SR01) if the memory contents are to be preserved. However, leaving this bit set to 0 for
longer than a few tenths of a microsecond can still cause data loss in the frame buffer. No
register settings are changed by performing this type of reset.
0: Forces synchronous reset and halt
1: Permits normal operation
Setting this bit to 0 commands the sequencer to perform a clear and then halt. Resetting
the sequencer via this bit can cause data loss in the frame buffer. No register settings are
changed by performing this type of reset.
0: Forces asynchronous reset
1: Permits normal operation
6
6
Reserved
5
5
Reserved
Sequencer Registers
4
4
3
3
2
2
Sequencer Register Index
Sync Reset Async Reset
Revision 1.3 11/24/99
1
1
0
0
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