M69030 Asiliant Technologies, M69030 Datasheet - Page 202

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

14-22
XR71
read-only at I/O address 3D7h with 3D6h set to Index 71h
shared by both pipelines A and B
The bits of this register indicate the state of each of these pins at the time the graphics controller is reset.
During a reset, the graphics controller does not drive these pins, thereby allowing them to either be pulled
high by relatively weak internal resistors, or to be pulled low by external resistors (4.7K recommended).
Instead, during reset, the graphics controller latches the state of these pins, and the latched values are used
by the graphics controller to provide a limited degree of hardware-based configuration of some features.
Some of these latched values directly affect the hardware, while others are simply reflected in this register
so as to be read by configuration software, usually the BIOS.
7
6
5
4
3
2
1
0
`efmp
A
&
B
CFG15

Pin CFG15
Pin CFG14
Pin CFG13
Pin CFG12
Pin CFG11
Pin CFG10
Pin CFG9
Pin CFG8
69030 Databook
(x)
7
Configuration Pins 1 Register
Reserved. An individual interpretation has not been assigned to this bit, and the hardware
does not interpret the state of the corresponding pin during reset.
Reserved for BIOS for use as bit 3 of a 4-bit code specifying the panel type.
Reserved for BIOS for use as bit 2 of a 4-bit code specifying the panel type.
Reserved for BIOS for use as bit 1 of a 4-bit code specifying the panel type.
Reserved for BIOS for use as bit 0 of a 4-bit code specifying the panel type.
Reserved. An individual interpretation has not been assigned to this bit, and the hardware
does not interpret the state of the corresponding pin during reset.
0: Indicates that the upper memory space has been configured to provide single-pipe dual-
endian support. Pipeline A’s memory space is repeated to provide both little-endian and a
big-endian address ranges.
1: Indicates that the upper memory space has been configured to provide little-endian dual-
pipe support. Both pipeline A’s and pipeline B’s memory spaces are provided, and only in
little endian.
Reserved. An individual interpretation has not been assigned to this bit, and the hardware
does not interpret the state of the corresponding pin during reset.
CFG14
(x)
6
CFG13
(x)
5
Extension Registers
CFG12
(x)
4
CFG11
(x)
3
CFG10
(x)
2
CFG9
Revision 1.3 11/24/99
(x)
1
CFG8
(x)
0