M69030 Asiliant Technologies, M69030 Datasheet - Page 377
M69030
Manufacturer Part Number
M69030
Description
Manufacturer
Asiliant Technologies
Datasheet
1.M69030.pdf
(387 pages)
Specifications of M69030
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed
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CHIPS
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M69030P
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MIT
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BitBLT Operation
E-15
Figure E-8: Pattern Data
(Always an 8x8 Array of Pixels)
The Pattern Address Register (BR05) is used to specify the address of the pattern data as an offset from
the beginning of the frame buffer at which the block of pattern data begins. The three least significant bits
of the address written to this register are ignored, because the address must be in terms of quadwords. This
is because the pattern must always be located on an address boundary equal to its size. Monochrome
patterns take up 8 bytes, or a single quadword of space, and therefore, must be located on a quadword
boundary. Similarly, color patterns with color depths of 8 and 16 bits per pixel must start on 64-byte and
128-byte boundaries, respectively. Color patterns with color depths of 24 bits per pixel must start on 256-
byte boundaries, despite the fact that the actual color data fills only 3 bytes per pixel.
Figures E-9, E-10, E.3-11, and E-12 show how monochrome, 8bpp, 16bpp, and 24bpp pattern data is
organized in memory.
Figure E-9: Monochrome Pattern Data -- Occupies a Single Quadword
Figure E-10: 8bpp Pattern Data -- Occupies 64 Bytes (8 Quadwords)
`efmp
69030 Databook
Revision 1.3 11/24/99
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