M69030 Asiliant Technologies, M69030 Datasheet - Page 134

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

9-32
CR31
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 31h
shadowed for pipelines A and B
7-4
3-0
`efmp
A
B

Reserved
Vertical Display End Bits 11-8
69030 Databook
7
Extended Vertical Display End Register
These bits should always be written with the value of 0.
The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the
last scanline within the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the
vertical display enable end is specified with a 10-bit value. The 8 least significant bits of
the vertical display enable end are supplied by bits 7-0 of the Vertical Display Enable End
Register (CR12), and the 2 most significant bits are supplied by bits 6 and 1 of the Overflow
Register (CR07). In standard VGA modes bits 3-0 of CR31 are not used.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical
display enable end is specified with a 12-bit value. The 8 least significant bits of the vertical
display enable end are supplied by bits 7-0 of the Vertical Display Enable End Register
(CR12), and the 4 most significant bits are supplied by these 4 bits of this register (CR31).
This 10-bit or 12-bit value should be programmed to be equal to the number of the last
scanline with in the active display area. Since the active display area always starts on the
0th scanline, this number should be equal to the total number of scanlines within the active
display area, minus 1.
6
Reserved
Reserved
5
CRT Controller Registers
4
3
Vertical Sync Start Bits 11-8
Vertical Sync Start Bits 11-8
2
Revision 1.3 11/24/99
1
0