M69030 Asiliant Technologies, M69030 Datasheet - Page 59

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

I/O and Memory Address Maps
5-5
Register Shadowing Schemes for Dual-Pipe
To answer the need to create two pixel pipelines that are both compatible with the VGA standard, a scheme
involving a combination of “sharing” and “shadowing” of registers accessed via the I/O space is used. To
accommodate different operating system driver architectures, another scheme of sharing and shadowing is
employed for registers accessed via the memory space.
Shared registers are generally used to support hardware that is shared by both pipelines, or that is meant
to be reassignable from one pipeline to the other. Shared registers are designed to be accessible to the
driver code controlling either pipe whether they are accessed via the I/O or memory-mapped register space
shadowing schemes.
Shadowed registers are generally used to support hardware that belongs exclusively to one pipeline or the
other. Each of the two shadows of a register are usually meant to be bit-for-bit identical to the other, and to
perform the same functions, but for different pipelines. Shadowed registers are generally intended to be
accessible only to the driver code controlling the functions of the pipeline to which that driver belongs, even
though the hardware controlling the shadowing schemes used in both I/O and memory-mapped register
spaces can be configured to allow the shadowed registers of both pipelines to be write-accessible at the
same time by a driver belonging to only one of the pipelines.
The I/O and memory-mapped register space shadowing schemes, do not apply to the PCI configuration
registers, which are accessible only via the PCI configuration space. Also, there is only one frame buffer,
and it is not put through any form of shadowing scheme.
I/O Space Register Shadowing
To ensure VGA compatibility for both pipelines, a “shadowing” scheme is used to allow the I/O-accessible
registers of both pipelines to be accessible by the host CPU at the usual I/O address locations. In essence,
the registers for each pipeline will be “swapped” into and out of the usual I/O locations, so that existing
software can be made to unknowingly program one and/or the other pipeline’s registers at any given time.
This I/O space shadowing scheme is controlled through the I/O Space Shadowing Register (IOSS) located
at I/O address 3CDh. Through this register it is possible to select one or the other of the pipelines’ I/O-
addressable registers to be accessible for reading, and it is possible to enable one or the other, or both, or
neither of the pipelines’ I/O-addressable registers to be accessible for writing.
`efmp
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69030 Databook
Revision 1.3 11/24/99