M69030 Asiliant Technologies, M69030 Datasheet - Page 31

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

B69030 and M69030 PCI/AGP Bus Interface (continued)
`efmp
BGA
Pin
M4
M3
M2
U2
R4
U1
R3
R2
R1
N3
N2
N1
H1
H2
G1
H3
G3
D1
G2
T3
T2
T1
P2
P1
F2
E1
F3
E2
F4
E3
P3
K3
F1
J1
J2
J3
J4

69030 Databook
mBGA
Pin
M4
M3
M2
G1
G3
G4
G5
M1
G2
P1
N2
N1
K5
K3
K2
K4
K1
H4
E2
H5
D2
D1
E3
C2
D3
E1
L5
L4
L3
L2
L1
F2
F1
F4
F5
F3
J6
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IDSEL
Name
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
In
In
In
In
In
Active
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Powered
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
Pin Descriptions
PCI/AGP Address/Data Bus
Address and data are multiplexed on the same pins. A
bus transaction consists of an address phase followed
by one or more data phases (both read and write bursts
are allowed by the bus definition).
The address phase is the clock cycle in which FRAME#
is asserted (AD0-31 contain a 32-bit physical address).
For I/O, the address is a byte address. For memory and
configuration, the address is a DWORD address. During
data phases AD0-7 contain the LSB and 24-31 contain
the MSB. Write data is stable and valid when IRDY# is
asserted; read data is stable and valid when TRDY# is
asserted. Data transfers only during those clocks when
both IRDY# and TRDY# are asserted.
Bus Command/Byte Enables. During the address phase
of a bus transaction, these pins define the bus command
(see list above). During the data phase, these pins are
byte enables that determine which byte lanes carry
meaningful data: byte 0 corresponds to AD0-7, byte 1 to
8-15, byte 2 to 16-23, and byte 3 to 24-31.
Initialization Device Select. Used as a chip select during
configuration read and write transactions
C/BE3-0 Command Type
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
-reserved-
-reserved-
Memory Read
Memory Write
-reserved-
-reserved-
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Read & Invalidate
Description
Revision 1.3 11/24/99
Supported
Y
Y
Y
Y
Y
Y
2-7