M69030 Asiliant Technologies, M69030 Datasheet - Page 205

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

XR81
read/write at I/O address 3D7h with index at I/O address 3D6h set to 81h
shadowed for pipelines A and B
7-5
4
3-0
`efmp
A
B

Reserved
VGA Standard Signal Delay Enable
Graphics System Color Depth
69030 Databook
7
Pixel Pipeline Configuration 1 Register
These bits always return the value of 0 when read.
0: The CRT Display Enable and CRT Blanking are delayed for compatibility with the VGA
standard. The behavior of CR00 remains compatible with the VGA standard, inasmuch as
the value placed there must be subtracted by 5. This is the default after reset.
1: The CRT Display Enable and CRT Blanking are not delayed. The behavior of CR00 is
altered in a way that is different from the VGA standard, inasmuch as the value placed there
is not to be subtracted by 5.
Note: This enables/disables the delay of signals relative to the CRT horizontal and vertical
sync signals. When the flat panel display engine is enabled (i.e., when bit 1 of FR01 is set
to 1), then this bit is ignored and no such delay takes place.
1 x x x
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
Reserved
Reserved
Bits
(000)
(000)
6
Configures the CRT pipeline for standard VGA text and graphics modes, and for 1bpp,
2bpp and 4bpp extended graphics modes. This is the default after reset.
Reserved
Configures the CRT pipeline for 8bpp extended graphics modes.
Reserved
Configures the CRT pipeline for 16bpp extended graphics modes wherein the graphics
data follows a fixed Targa-compatible 5-5-5 RGB format.
Configures the CRT pipeline for 16bpp extended graphics modes wherein the graphics
data follows a fixed XGA-compatible 5-6-5 RGB format.
Configures the CRT pipeline for packed 24bpp extended graphics modes wherein only
3 bytes are allocated for each pixel.
Configures the CRT pipeline for non-packed 24bpp (32bpp) extended graphics modes
wherein 4 bytes are allocated for each pixel, so that the graphics data for each pixel is
doubleword-aligned. The 4th byte allocated for each pixel is unused.
Reserved
5
Extension Registers
VGA Std
VGA Std
Delay
Delay
Color Depth Selected for Graphics System
(0)
(0)
4
3
Graphics System Color Depth
Graphics System Color Depth
2
(0000)
(0000)
Revision 1.3 11/24/99
1
0
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