M69030 Asiliant Technologies, M69030 Datasheet - Page 258

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

15-20
FR12
read/write at I/O address 3D1h with index at I/O address 3D0h set to 12h
shadowed only for pipeline A
7-6
5
4
3
`efmp
A
B

FP Data Width
Force FP Data Signals High during Vertical Blank
Force FP HSync (LP) during Vertical Blank
FP Display Enable (FP Blank#) Select
69030 Databook
7
FP Data Width
FP Format 2 Register
(00)
0: Flat panel data output signals are not forced high during vertical blanking.
1: Flat panel data output signals are forced high during vertical blanking.
0: FP Display Enable output is generated by inverting both FP Vertical and Horizontal
Blank therefore FP Display Enable will not toggle active during Vertical Blank time. FP
HSync (LP) is not generated during Vertical Blank except when bit 3 is set to 1. This is the
default after reset.
1: FP Display Enable output is generated by inverting FP Horizontal Blank only therefore
FP Display Enable will be active during Vertical Blank time. FP HSync (LP) will also be
active during Vertical Blank.
This bit should be set only for SS panels which require FP HSync (LP) to be active during
vertical blank time when bit 3 is 0. This bit should be reset when using DD panels or when
bit 3 is 1.
0: The FP Display Enable is inactive during vertical blank time because the output comes
from inverting both the FP Vertical and Horizontal blank. FP HSync is not generated during
vertical blank except when bit 4 is set to 1. In 480-line DD panels, this option will generate
exactly 240 FP HSync (LP) pulses. This is the default after reset.
1: The FP Display Enable is active during Vertical blank time since the output comes from
inverting the FP Horizontal Blank enable. FP HSync will also be active during vertical
blank.
This bit controls FP Display Enable (FP Blank#) generation. This bit also affects FP HSync
(LP) generation.
Bits
7 6
0 0
0 1
1 0
1 1
6
16-bit panel data width. For color TFT panel this is the 565
RGB interface. This is the default after reset.
24-bit panel data width. For color the TFT panel this is the
888 RGB interface. This setting can also be used for the 24-
bit color STN-DD panel.
Reserved.
36-bit panel data width (TFT panels only). Program 000 in
shift clock divide bits of FR10.
Data High
Force FP
5
not shadowed for this pipeline
Flat Panel Registers
HSYNC
Force
4
FP Data Width
FP Blank#
Select
(0)
3
Clk Mask
STN-DD
(0)
2
Clock Mask
Revision 1.3 11/24/99
(0)
1
Clock Divide
(0)
0